OpenCores

Rev 18	Rev 20
Line 35...	Line 35...
`//// ////`	`//// ////`
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`

`// CVS Log`	`// CVS Log`
`//`	`//`
`// $Id: mc_rf.v,v 1.6 2001-12-11 02:47:19 rudi Exp $`	`// $Id: mc_rf.v,v 1.7 2001-12-21 05:09:29 rudi Exp $`
`//`	`//`
`// $Date: 2001-12-11 02:47:19 $`	`// $Date: 2001-12-21 05:09:29 $`
`// $Revision: 1.6 $`	`// $Revision: 1.7 $`
`// $Author: rudi $`	`// $Author: rudi $`
`// $Locker: $`	`// $Locker: $`
`// $State: Exp $`	`// $State: Exp $`
`//`	`//`
`// Change History:`	`// Change History:`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.6 2001/12/11 02:47:19 rudi`
	`//`
	`// - Made some changes not to expect clock during reset ...`
	`//`
`// Revision 1.5 2001/11/29 02:16:28 rudi`	`// Revision 1.5 2001/11/29 02:16:28 rudi`
`//`	`//`
`//`	`//`
`// - More Synthesis cleanup, mostly for speed`	`// - More Synthesis cleanup, mostly for speed`
`// - Several bug fixes`	`// - Several bug fixes`
Line 113...	Line 117...

`csc, tms, poc,`	`csc, tms, poc,`
`sp_csc, sp_tms, cs,`	`sp_csc, sp_tms, cs,`
`mc_data_i, mc_sts, mc_vpen, fs,`	`mc_data_i, mc_sts, mc_vpen, fs,`

`cs_le, cs_need_rfr, ref_int, rfr_ps_val, init_req,`	`cs_le_d, cs_le, cs_need_rfr, ref_int, rfr_ps_val, init_req,`
`init_ack, lmr_req, lmr_ack,`	`init_ack, lmr_req, lmr_ack,`
`spec_req_cs`	`spec_req_cs`
`);`	`);`

`input clk, rst;`	`input clk, rst;`
Line 147...	Line 151...
`input [31:0] mc_data_i;`	`input [31:0] mc_data_i;`
`input mc_sts;`	`input mc_sts;`
`output mc_vpen;`	`output mc_vpen;`
`output fs;`	`output fs;`

	`input cs_le_d;`
`input cs_le;`	`input cs_le;`

`output [7:0] cs_need_rfr; // Indicates which chip selects have SDRAM`	`output [7:0] cs_need_rfr; // Indicates which chip selects have SDRAM`
`// attached and need to be refreshed`	`// attached and need to be refreshed`
`output [2:0] ref_int; // Refresh Interval`	`output [2:0] ref_int; // Refresh Interval`
Line 345...	Line 350...
`if(!wb_cyc_i) wp_err <= #1 1'b0;`	`if(!wb_cyc_i) wp_err <= #1 1'b0;`

`always @(posedge clk or posedge rst)`	`always @(posedge clk or posedge rst)`
`if(rst) csc <= #1 32'h0;`	`if(rst) csc <= #1 32'h0;`
`else`	`else`
`if(cs_le & wb_cyc_i & wb_stb_i)`	`if(cs_le_d & wb_cyc_i & wb_stb_i)`
`begin`	`begin`
`if(cs0) csc <= #1 csc0;`	`if(cs0) csc <= #1 csc0;`
`else`	`else`
`if(cs1) csc <= #1 csc1;`	`if(cs1) csc <= #1 csc1;`
`else`	`else`
Line 366...	Line 371...
`end`	`end`

`always @(posedge clk or posedge rst)`	`always @(posedge clk or posedge rst)`
`if(rst) tms <= #1 32'hffff_ffff;`	`if(rst) tms <= #1 32'hffff_ffff;`
`else`	`else`
`if((cs_le \| rf_we) & wb_cyc_i & wb_stb_i)`	`if((cs_le_d \| rf_we) & wb_cyc_i & wb_stb_i)`
`begin`	`begin`
`if(cs0) tms <= #1 tms0;`	`if(cs0) tms <= #1 tms0;`
`else`	`else`
`if(cs1) tms <= #1 tms1;`	`if(cs1) tms <= #1 tms1;`
`else`	`else`
Line 387...	Line 392...
`end`	`end`

`always @(posedge clk or posedge rst)`	`always @(posedge clk or posedge rst)`
`if(rst) sp_csc <= #1 32'h0;`	`if(rst) sp_csc <= #1 32'h0;`
`else`	`else`
`if(cs_le & wb_cyc_i & wb_stb_i)`	`if(cs_le_d & wb_cyc_i & wb_stb_i)`
`begin`	`begin`
`if(spec_req_cs[0]) sp_csc <= #1 csc0;`	`if(spec_req_cs[0]) sp_csc <= #1 csc0;`
`else`	`else`
`if(spec_req_cs[1]) sp_csc <= #1 csc1;`	`if(spec_req_cs[1]) sp_csc <= #1 csc1;`
`else`	`else`
Line 408...	Line 413...
`end`	`end`

`always @(posedge clk or posedge rst)`	`always @(posedge clk or posedge rst)`
`if(rst) sp_tms <= #1 32'hffff_ffff;`	`if(rst) sp_tms <= #1 32'hffff_ffff;`
`else`	`else`
`if((cs_le \| rf_we) & wb_cyc_i & wb_stb_i)`	`if((cs_le_d \| rf_we) & wb_cyc_i & wb_stb_i)`
`begin`	`begin`
`if(spec_req_cs[0]) sp_tms <= #1 tms0;`	`if(spec_req_cs[0]) sp_tms <= #1 tms0;`
`else`	`else`
`if(spec_req_cs[1]) sp_tms <= #1 tms1;`	`if(spec_req_cs[1]) sp_tms <= #1 tms1;`
`else`	`else`

Line 35...

////                                                             ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////

//  CVS Log

//  CVS Log

//

//

//  $Id: mc_rf.v,v 1.6 2001-12-11 02:47:19 rudi Exp $

//  $Id: mc_rf.v,v 1.7 2001-12-21 05:09:29 rudi Exp $

//

//

//  $Date: 2001-12-11 02:47:19 $

//  $Date: 2001-12-21 05:09:29 $

//  $Revision: 1.6 $

//  $Revision: 1.7 $

//  $Author: rudi $

//  $Author: rudi $

//  $Locker:  $

//  $Locker:  $

//  $State: Exp $

//  $State: Exp $

//

//

// Change History:

// Change History:

//               $Log: not supported by cvs2svn $

//               $Log: not supported by cvs2svn $

//               Revision 1.6  2001/12/11 02:47:19  rudi

//

//               - Made some changes not to expect clock during reset ...

//

//               Revision 1.5  2001/11/29 02:16:28  rudi

//               Revision 1.5  2001/11/29 02:16:28  rudi

//

//

//

//

//               - More Synthesis cleanup, mostly for speed

//               - More Synthesis cleanup, mostly for speed

//               - Several bug fixes

//               - Several bug fixes

Line 113...

Line 117...

        csc, tms, poc,

        csc, tms, poc,

        sp_csc, sp_tms, cs,

        sp_csc, sp_tms, cs,

        mc_data_i, mc_sts, mc_vpen, fs,

        mc_data_i, mc_sts, mc_vpen, fs,

        cs_le, cs_need_rfr, ref_int, rfr_ps_val, init_req,

        cs_le_d, cs_le, cs_need_rfr, ref_int, rfr_ps_val, init_req,

        init_ack, lmr_req, lmr_ack,

        init_ack, lmr_req, lmr_ack,

        spec_req_cs

        spec_req_cs

);

);

input           clk, rst;

input           clk, rst;

Line 147...

Line 151...

input   [31:0]   mc_data_i;

input   [31:0]   mc_data_i;

input           mc_sts;

input           mc_sts;

output          mc_vpen;

output          mc_vpen;

output          fs;

output          fs;

input           cs_le_d;

input           cs_le;

input           cs_le;

output  [7:0]    cs_need_rfr;    // Indicates which chip selects have SDRAM

output  [7:0]    cs_need_rfr;    // Indicates which chip selects have SDRAM

                                // attached and need to be refreshed

                                // attached and need to be refreshed

output  [2:0]    ref_int;        // Refresh Interval

output  [2:0]    ref_int;        // Refresh Interval

Line 345...

Line 350...

        if(!wb_cyc_i)   wp_err <= #1 1'b0;

        if(!wb_cyc_i)   wp_err <= #1 1'b0;

always @(posedge clk or posedge rst)

always @(posedge clk or posedge rst)

        if(rst)         csc <= #1 32'h0;

        if(rst)         csc <= #1 32'h0;

        else

        else

        if(cs_le & wb_cyc_i & wb_stb_i)

        if(cs_le_d & wb_cyc_i & wb_stb_i)

           begin

           begin

                if(cs0) csc <= #1 csc0;

                if(cs0) csc <= #1 csc0;

                else

                else

                if(cs1) csc <= #1 csc1;

                if(cs1) csc <= #1 csc1;

                else

                else

Line 366...

Line 371...

end

end

always @(posedge clk or posedge rst)

always @(posedge clk or posedge rst)

        if(rst)         tms <= #1 32'hffff_ffff;

        if(rst)         tms <= #1 32'hffff_ffff;

        else

        else

        if((cs_le | rf_we) & wb_cyc_i & wb_stb_i)

        if((cs_le_d | rf_we) & wb_cyc_i & wb_stb_i)

           begin

           begin

                if(cs0) tms <= #1 tms0;

                if(cs0) tms <= #1 tms0;

                else

                else

                if(cs1) tms <= #1 tms1;

                if(cs1) tms <= #1 tms1;

                else

                else

Line 387...

Line 392...

end

end

always @(posedge clk or posedge rst)

always @(posedge clk or posedge rst)

        if(rst)                         sp_csc <= #1 32'h0;

        if(rst)                         sp_csc <= #1 32'h0;

        else

        else

        if(cs_le & wb_cyc_i & wb_stb_i)

        if(cs_le_d & wb_cyc_i & wb_stb_i)

           begin

           begin

                if(spec_req_cs[0])       sp_csc <= #1 csc0;

                if(spec_req_cs[0])       sp_csc <= #1 csc0;

                else

                else

                if(spec_req_cs[1])      sp_csc <= #1 csc1;

                if(spec_req_cs[1])      sp_csc <= #1 csc1;

                else

                else

Line 408...

Line 413...

end

end

always @(posedge clk or posedge rst)

always @(posedge clk or posedge rst)

        if(rst)                         sp_tms <= #1 32'hffff_ffff;

        if(rst)                         sp_tms <= #1 32'hffff_ffff;

        else

        else

        if((cs_le | rf_we) & wb_cyc_i & wb_stb_i)

        if((cs_le_d | rf_we) & wb_cyc_i & wb_stb_i)

           begin

           begin

                if(spec_req_cs[0])       sp_tms <= #1 tms0;

                if(spec_req_cs[0])       sp_tms <= #1 tms0;

                else

                else

                if(spec_req_cs[1])      sp_tms <= #1 tms1;

                if(spec_req_cs[1])      sp_tms <= #1 tms1;

                else

                else

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