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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: mc_rf.v,v 1.1 2001-07-29 07:34:41 rudi Exp $
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// $Id: mc_rf.v,v 1.2 2001-08-10 08:16:21 rudi Exp $
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//
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//
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// $Date: 2001-07-29 07:34:41 $
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// $Date: 2001-08-10 08:16:21 $
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// $Revision: 1.1 $
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// $Revision: 1.2 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2001/07/29 07:34:41 rudi
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//
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//
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// 1) Changed Directory Structure
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// 2) Fixed several minor bugs
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//
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// Revision 1.3 2001/06/12 15:19:49 rudi
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// Revision 1.3 2001/06/12 15:19:49 rudi
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//
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//
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//
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//
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// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
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// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
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//
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//
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| Line 206... |
Line 212... |
//
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//
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assign wb_err_o = 1'b0;
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assign wb_err_o = 1'b0;
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always @(posedge clk)
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always @(posedge clk)
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if(wb_cyc_i & wb_stb_i & `REG_SEL & !wb_we_i)
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if(wb_cyc_i & wb_stb_i & `MC_REG_SEL & !wb_we_i)
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case(wb_addr_i[6:2]) // synopsys full_case parallel_case
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case(wb_addr_i[6:2]) // synopsys full_case parallel_case
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5'h0: rf_dout <= #1 csr;
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5'h0: rf_dout <= #1 csr;
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5'h1: rf_dout <= #1 poc;
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5'h1: rf_dout <= #1 poc;
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5'h2: rf_dout <= #1 csc_mask;
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5'h2: rf_dout <= #1 csc_mask;
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| Line 235... |
Line 241... |
////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// WISHBONE Register Write logic
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// WISHBONE Register Write logic
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//
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//
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assign rf_we = `REG_SEL & wb_we_i & wb_cyc_i & wb_stb_i;
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assign rf_we = `MC_REG_SEL & wb_we_i & wb_cyc_i & wb_stb_i;
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always @(posedge clk or negedge rst)
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always @(posedge clk or negedge rst)
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if(!rst) csr_r2 <= #1 8'h0;
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if(!rst) csr_r2 <= #1 8'h0;
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else
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else
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if(rf_we & (wb_addr_i[6:2] == 5'h0) )
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if(rf_we & (wb_addr_i[6:2] == 5'h0) )
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| Line 271... |
Line 277... |
//
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//
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// WISHBONE Register Ack logic
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// WISHBONE Register Ack logic
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//
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//
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always @(posedge clk)
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always @(posedge clk)
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ack_r <= #1 `REG_SEL & wb_cyc_i & wb_stb_i & !ack_r & !wb_ack_o;
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ack_r <= #1 `MC_REG_SEL & wb_cyc_i & wb_stb_i & !ack_r & !wb_ack_o;
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always @(posedge clk)
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always @(posedge clk)
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wb_ack_o <= #1 ack_r;
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wb_ack_o <= #1 ack_r;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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| Line 351... |
Line 357... |
3'h5: sp_tms <= #1 tms5;
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3'h5: sp_tms <= #1 tms5;
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3'h6: sp_tms <= #1 tms6;
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3'h6: sp_tms <= #1 tms6;
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3'h7: sp_tms <= #1 tms7;
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3'h7: sp_tms <= #1 tms7;
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endcase
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endcase
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assign cs_need_rfr[0] = csc0[0] & (csc0[3:1] == `MEM_TYPE_SDRAM);
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assign cs_need_rfr[0] = csc0[0] & (csc0[3:1] == `MC_MEM_TYPE_SDRAM);
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assign cs_need_rfr[1] = csc1[0] & (csc1[3:1] == `MEM_TYPE_SDRAM);
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assign cs_need_rfr[1] = csc1[0] & (csc1[3:1] == `MC_MEM_TYPE_SDRAM);
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assign cs_need_rfr[2] = csc2[0] & (csc2[3:1] == `MEM_TYPE_SDRAM);
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assign cs_need_rfr[2] = csc2[0] & (csc2[3:1] == `MC_MEM_TYPE_SDRAM);
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assign cs_need_rfr[3] = csc3[0] & (csc3[3:1] == `MEM_TYPE_SDRAM);
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assign cs_need_rfr[3] = csc3[0] & (csc3[3:1] == `MC_MEM_TYPE_SDRAM);
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assign cs_need_rfr[4] = csc4[0] & (csc4[3:1] == `MEM_TYPE_SDRAM);
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assign cs_need_rfr[4] = csc4[0] & (csc4[3:1] == `MC_MEM_TYPE_SDRAM);
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assign cs_need_rfr[5] = csc5[0] & (csc5[3:1] == `MEM_TYPE_SDRAM);
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assign cs_need_rfr[5] = csc5[0] & (csc5[3:1] == `MC_MEM_TYPE_SDRAM);
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assign cs_need_rfr[6] = csc6[0] & (csc6[3:1] == `MEM_TYPE_SDRAM);
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assign cs_need_rfr[6] = csc6[0] & (csc6[3:1] == `MC_MEM_TYPE_SDRAM);
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assign cs_need_rfr[7] = csc7[0] & (csc7[3:1] == `MEM_TYPE_SDRAM);
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assign cs_need_rfr[7] = csc7[0] & (csc7[3:1] == `MC_MEM_TYPE_SDRAM);
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assign ref_int = csr_r[10:8];
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assign ref_int = csr_r[10:8];
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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| Line 455... |
Line 461... |
.lmr_ack( lmr_ack0 ),
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.lmr_ack( lmr_ack0 ),
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.init_req( init_req0 ),
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.init_req( init_req0 ),
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.init_ack( init_ack0 )
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.init_ack( init_ack0 )
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);
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);
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`ifdef HAVE_CS1
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`ifdef MC_HAVE_CS1
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mc_cs_rf #(3'h1) u1(
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mc_cs_rf #(3'h1) u1(
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.clk( clk ),
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.clk( clk ),
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.rst( rst ),
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.rst( rst ),
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.wb_we_i( wb_we_i ),
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.wb_we_i( wb_we_i ),
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.din( wb_data_i ),
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.din( wb_data_i ),
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| Line 495... |
Line 501... |
.init_req( init_req1 ),
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.init_req( init_req1 ),
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.init_ack( init_ack1 )
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.init_ack( init_ack1 )
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);
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);
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`endif
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`endif
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`ifdef HAVE_CS2
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`ifdef MC_HAVE_CS2
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mc_cs_rf #(3'h2) u2(
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mc_cs_rf #(3'h2) u2(
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.clk( clk ),
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.clk( clk ),
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.rst( rst ),
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.rst( rst ),
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.wb_we_i( wb_we_i ),
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.wb_we_i( wb_we_i ),
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.din( wb_data_i ),
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.din( wb_data_i ),
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| Line 535... |
Line 541... |
.init_req( init_req2 ),
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.init_req( init_req2 ),
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.init_ack( init_ack2 )
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.init_ack( init_ack2 )
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);
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);
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`endif
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`endif
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`ifdef HAVE_CS3
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`ifdef MC_HAVE_CS3
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mc_cs_rf #(3'h3) u3(
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mc_cs_rf #(3'h3) u3(
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.clk( clk ),
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.clk( clk ),
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.rst( rst ),
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.rst( rst ),
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.wb_we_i( wb_we_i ),
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.wb_we_i( wb_we_i ),
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.din( wb_data_i ),
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.din( wb_data_i ),
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| Line 575... |
Line 581... |
.init_req( init_req3 ),
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.init_req( init_req3 ),
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.init_ack( init_ack3 )
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.init_ack( init_ack3 )
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);
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);
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`endif
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`endif
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`ifdef HAVE_CS4
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`ifdef MC_HAVE_CS4
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mc_cs_rf #(3'h4) u4(
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mc_cs_rf #(3'h4) u4(
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.clk( clk ),
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.clk( clk ),
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.rst( rst ),
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.rst( rst ),
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.wb_we_i( wb_we_i ),
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.wb_we_i( wb_we_i ),
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.din( wb_data_i ),
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.din( wb_data_i ),
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| Line 615... |
Line 621... |
.init_req( init_req4 ),
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.init_req( init_req4 ),
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.init_ack( init_ack4 )
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.init_ack( init_ack4 )
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);
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);
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`endif
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`endif
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`ifdef HAVE_CS5
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`ifdef MC_HAVE_CS5
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mc_cs_rf #(3'h5) u5(
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mc_cs_rf #(3'h5) u5(
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.clk( clk ),
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.clk( clk ),
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.rst( rst ),
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.rst( rst ),
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.wb_we_i( wb_we_i ),
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.wb_we_i( wb_we_i ),
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.din( wb_data_i ),
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.din( wb_data_i ),
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| Line 655... |
Line 661... |
.init_req( init_req5 ),
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.init_req( init_req5 ),
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.init_ack( init_ack5 )
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.init_ack( init_ack5 )
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);
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);
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`endif
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`endif
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`ifdef HAVE_CS6
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`ifdef MC_HAVE_CS6
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mc_cs_rf #(3'h6) u6(
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mc_cs_rf #(3'h6) u6(
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.clk( clk ),
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.clk( clk ),
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.rst( rst ),
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.rst( rst ),
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.wb_we_i( wb_we_i ),
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.wb_we_i( wb_we_i ),
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.din( wb_data_i ),
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.din( wb_data_i ),
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| Line 695... |
Line 701... |
.init_req( init_req6 ),
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.init_req( init_req6 ),
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.init_ack( init_ack6 )
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.init_ack( init_ack6 )
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);
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);
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`endif
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`endif
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`ifdef HAVE_CS7
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`ifdef MC_HAVE_CS7
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mc_cs_rf #(3'h7) u7(
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mc_cs_rf #(3'h7) u7(
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.clk( clk ),
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.clk( clk ),
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.rst( rst ),
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.rst( rst ),
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.wb_we_i( wb_we_i ),
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.wb_we_i( wb_we_i ),
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.din( wb_data_i ),
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.din( wb_data_i ),
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