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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: mc_timing.v,v 1.3 2001-09-02 02:28:28 rudi Exp $
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// $Id: mc_timing.v,v 1.4 2001-09-24 00:38:21 rudi Exp $
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//
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//
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// $Date: 2001-09-02 02:28:28 $
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// $Date: 2001-09-24 00:38:21 $
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// $Revision: 1.3 $
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// $Revision: 1.4 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2001/09/02 02:28:28 rudi
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//
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// Many fixes for minor bugs that showed up in gate level simulations.
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//
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// Revision 1.2 2001/08/10 08:16:21 rudi
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// Revision 1.2 2001/08/10 08:16:21 rudi
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//
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//
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// - Changed IO names to be more clear.
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// - Changed IO names to be more clear.
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// - Uniquifyed define names to be core specific.
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// - Uniquifyed define names to be core specific.
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// - Removed "Refresh Early" configuration
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// - Removed "Refresh Early" configuration
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Line 417... |
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always @(posedge clk)
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always @(posedge clk)
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rsts <= #1 rsts1;
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rsts <= #1 rsts1;
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// Control Signals Output Enable
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// Control Signals Output Enable
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always @(posedge clk)
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always @(posedge clk or posedge rst)
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if(!rst) mc_c_oe <= #1 1'b0;
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if(rst) mc_c_oe <= #1 1'b0;
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else mc_c_oe <= #1 mc_c_oe_d;
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else mc_c_oe <= #1 mc_c_oe_d;
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always @(posedge clk or negedge rsts)
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always @(posedge clk or posedge rsts)
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if(!rsts) mc_le <= #1 1'b0;
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if(rsts) mc_le <= #1 1'b0;
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else mc_le <= #1 ~mc_le;
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else mc_le <= #1 ~mc_le;
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always @(posedge clk)
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always @(posedge clk)
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pack_le0 <= #1 pack_le0_d;
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pack_le0 <= #1 pack_le0_d;
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Line 516... |
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always @(posedge clk)
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always @(posedge clk)
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lookup_ready2 <= #1 lookup_ready1;
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lookup_ready2 <= #1 lookup_ready1;
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// Keep Track if it is a SDRAM write cycle
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// Keep Track if it is a SDRAM write cycle
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always @(posedge clk or negedge rst)
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always @(posedge clk or posedge rst)
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if(!rst) wr_cycle <= #1 1'b0;
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if(rst) wr_cycle <= #1 1'b0;
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else
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else
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if(wr_set) wr_cycle <= #1 1'b1;
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if(wr_set) wr_cycle <= #1 1'b1;
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else
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else
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if(wr_clr) wr_cycle <= #1 1'b0;
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if(wr_clr) wr_cycle <= #1 1'b0;
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// Track when a cycle is *still* active
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// Track when a cycle is *still* active
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always @(posedge clk or negedge rst)
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always @(posedge clk or posedge rst)
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if(!rst) wb_cycle <= #1 1'b0;
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if(rst) wb_cycle <= #1 1'b0;
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else
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else
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if(wb_cycle_set) wb_cycle <= #1 1'b1;
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if(wb_cycle_set) wb_cycle <= #1 1'b1;
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else
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else
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if(!wb_cyc_i) wb_cycle <= #1 1'b0;
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if(!wb_cyc_i) wb_cycle <= #1 1'b0;
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// Track ack's for read cycles
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// Track ack's for read cycles
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always @(posedge clk or negedge rst)
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always @(posedge clk or posedge rst)
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if(!rst) ack_cnt <= #1 4'h0;
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if(rst) ack_cnt <= #1 4'h0;
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else
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else
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if(!wb_read_go & !wb_write_go) ack_cnt <= #1 4'h0;
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if(!wb_read_go & !wb_write_go) ack_cnt <= #1 4'h0;
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else
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else
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if(dv & !mem_ack_s) ack_cnt <= #1 ack_cnt + 4'h1;
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if(dv & !mem_ack_s) ack_cnt <= #1 ack_cnt + 4'h1;
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else
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else
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Line 565... |
rfr_ack_r <= #1 rfr_ack;
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rfr_ack_r <= #1 rfr_ack;
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// Suspend Select Logic
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// Suspend Select Logic
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assign susp_sel = susp_sel_r | susp_sel_set;
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assign susp_sel = susp_sel_r | susp_sel_set;
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always @(posedge clk or negedge rst)
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always @(posedge clk or posedge rst)
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if(!rst) susp_sel_r <= #1 0;
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if(rst) susp_sel_r <= #1 0;
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else
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else
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if(susp_sel_set) susp_sel_r <= #1 1'b1;
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if(susp_sel_set) susp_sel_r <= #1 1'b1;
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else
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else
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if(susp_sel_clr) susp_sel_r <= #1 1'b0;
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if(susp_sel_clr) susp_sel_r <= #1 1'b0;
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Line 612... |
wire [3:0] twrp;
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wire [3:0] twrp;
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assign twrp = tms_x[16:15] + tms_x[23:20];
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assign twrp = tms_x[16:15] + tms_x[23:20];
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// SDRAM Memories timing tracker
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// SDRAM Memories timing tracker
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always @(posedge clk or negedge rst)
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always @(posedge clk or posedge rst)
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`ifdef MC_POR_DELAY
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`ifdef MC_POR_DELAY
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if(!rst) timer <= #1 `MC_POR_DELAY_VAL ;
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if(rst) timer <= #1 `MC_POR_DELAY_VAL ;
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else
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else
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`endif
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`endif
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if(tmr_ld_twr2) timer <= #1 { 4'h0, tms_x[15:12] };
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if(tmr_ld_twr2) timer <= #1 { 4'h0, tms_x[15:12] };
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else
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else
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if(tmr_ld_trdz) timer <= #1 { 4'h0, tms_x[11:8] };
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if(tmr_ld_trdz) timer <= #1 { 4'h0, tms_x[11:8] };
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Line 685... |
////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Main State Machine
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// Main State Machine
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//
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//
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always @(posedge clk or negedge rst)
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always @(posedge clk or posedge rst)
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`ifdef MC_POR_DELAY
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`ifdef MC_POR_DELAY
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if(!rst) state <= #1 POR;
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if(rst) state <= #1 POR;
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`else
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`else
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if(!rst) state <= #1 IDLE;
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if(rst) state <= #1 IDLE;
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`endif
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`endif
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else state <= #1 next_state;
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else state <= #1 next_state;
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always @(state or cs_a or
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always @(state or cs_a or
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twd_is_zero or wb_stb_i or
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twd_is_zero or wb_stb_i or
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