| Line 35... |
Line 35... |
//// ////
|
//// ////
|
/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
|
|
// CVS Log
|
// CVS Log
|
//
|
//
|
// $Id: mc_timing.v,v 1.4 2001-09-24 00:38:21 rudi Exp $
|
// $Id: mc_timing.v,v 1.5 2001-11-29 02:16:28 rudi Exp $
|
//
|
//
|
// $Date: 2001-09-24 00:38:21 $
|
// $Date: 2001-11-29 02:16:28 $
|
// $Revision: 1.4 $
|
// $Revision: 1.5 $
|
// $Author: rudi $
|
// $Author: rudi $
|
// $Locker: $
|
// $Locker: $
|
// $State: Exp $
|
// $State: Exp $
|
//
|
//
|
// Change History:
|
// Change History:
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.4 2001/09/24 00:38:21 rudi
|
|
//
|
|
// Changed Reset to be active high and async.
|
|
//
|
// Revision 1.3 2001/09/02 02:28:28 rudi
|
// Revision 1.3 2001/09/02 02:28:28 rudi
|
//
|
//
|
// Many fixes for minor bugs that showed up in gate level simulations.
|
// Many fixes for minor bugs that showed up in gate level simulations.
|
//
|
//
|
// Revision 1.2 2001/08/10 08:16:21 rudi
|
// Revision 1.2 2001/08/10 08:16:21 rudi
|
| Line 209... |
Line 213... |
// Defines & Parameters
|
// Defines & Parameters
|
//
|
//
|
|
|
// Number of states: 66
|
// Number of states: 66
|
parameter [65:0] // synopsys enum state
|
parameter [65:0] // synopsys enum state
|
|
// 6666666555555555544444444443333333333222222222211111111110000000000
|
|
// 6543210987654321098765432109876543210987654321098765432109876543210
|
POR = 66'b000000000000000000000000000000000000000000000000000000000000000001,
|
POR = 66'b000000000000000000000000000000000000000000000000000000000000000001,
|
IDLE = 66'b000000000000000000000000000000000000000000000000000000000000000010,
|
IDLE = 66'b000000000000000000000000000000000000000000000000000000000000000010,
|
IDLE_T = 66'b000000000000000000000000000000000000000000000000000000000000000100,
|
IDLE_T = 66'b000000000000000000000000000000000000000000000000000000000000000100,
|
IDLE_T2 = 66'b000000000000000000000000000000000000000000000000000000000000001000,
|
IDLE_T2 = 66'b000000000000000000000000000000000000000000000000000000000000001000,
|
PRECHARGE = 66'b000000000000000000000000000000000000000000000000000000000000010000,
|
PRECHARGE = 66'b000000000000000000000000000000000000000000000000000000000000010000,
|
|
|
PRECHARGE_W = 66'b000000000000000000000000000000000000000000000000000000000000100000,
|
PRECHARGE_W = 66'b000000000000000000000000000000000000000000000000000000000000100000,
|
ACTIVATE = 66'b000000000000000000000000000000000000000000000000000000000001000000,
|
ACTIVATE = 66'b000000000000000000000000000000000000000000000000000000000001000000,
|
ACTIVATE_W = 66'b000000000000000000000000000000000000000000000000000000000010000000,
|
ACTIVATE_W = 66'b000000000000000000000000000000000000000000000000000000000010000000,
|
SD_RD_WR = 66'b000000000000000000000000000000000000000000000000000000000100000000,
|
SD_RD_WR = 66'b000000000000000000000000000000000000000000000000000000000100000000,
|
SD_RD = 66'b000000000000000000000000000000000000000000000000000000001000000000,
|
SD_RD = 66'b000000000000000000000000000000000000000000000000000000001000000000,
|
|
|
SD_RD_W = 66'b000000000000000000000000000000000000000000000000000000010000000000,
|
SD_RD_W = 66'b000000000000000000000000000000000000000000000000000000010000000000,
|
SD_RD_LOOP = 66'b000000000000000000000000000000000000000000000000000000100000000000,
|
SD_RD_LOOP = 66'b000000000000000000000000000000000000000000000000000000100000000000,
|
|
|
SD_RD_W2 = 66'b000000000000000000000000000000000000000000000000000001000000000000,
|
SD_RD_W2 = 66'b000000000000000000000000000000000000000000000000000001000000000000,
|
SD_WR = 66'b000000000000000000000000000000000000000000000000000010000000000000,
|
SD_WR = 66'b000000000000000000000000000000000000000000000000000010000000000000,
|
SD_WR_W = 66'b000000000000000000000000000000000000000000000000000100000000000000,
|
SD_WR_W = 66'b000000000000000000000000000000000000000000000000000100000000000000,
|
|
|
BT = 66'b000000000000000000000000000000000000000000000000001000000000000000,
|
BT = 66'b000000000000000000000000000000000000000000000000001000000000000000,
|
BT_W = 66'b000000000000000000000000000000000000000000000000010000000000000000,
|
BT_W = 66'b000000000000000000000000000000000000000000000000010000000000000000,
|
REFR = 66'b000000000000000000000000000000000000000000000000100000000000000000,
|
REFR = 66'b000000000000000000000000000000000000000000000000100000000000000000,
|
LMR0 = 66'b000000000000000000000000000000000000000000000001000000000000000000,
|
LMR0 = 66'b000000000000000000000000000000000000000000000001000000000000000000,
|
LMR1 = 66'b000000000000000000000000000000000000000000000010000000000000000000,
|
LMR1 = 66'b000000000000000000000000000000000000000000000010000000000000000000,
|
|
|
LMR2 = 66'b000000000000000000000000000000000000000000000100000000000000000000,
|
LMR2 = 66'b000000000000000000000000000000000000000000000100000000000000000000,
|
INIT0 = 66'b000000000000000000000000000000000000000000001000000000000000000000,
|
INIT0 = 66'b000000000000000000000000000000000000000000001000000000000000000000,
|
INIT = 66'b000000000000000000000000000000000000000000010000000000000000000000,
|
INIT = 66'b000000000000000000000000000000000000000000010000000000000000000000,
|
INIT_W = 66'b000000000000000000000000000000000000000000100000000000000000000000,
|
INIT_W = 66'b000000000000000000000000000000000000000000100000000000000000000000,
|
INIT_REFR1 = 66'b000000000000000000000000000000000000000001000000000000000000000000,
|
INIT_REFR1 = 66'b000000000000000000000000000000000000000001000000000000000000000000,
|
|
|
INIT_REFR1_W = 66'b000000000000000000000000000000000000000010000000000000000000000000,
|
INIT_REFR1_W = 66'b000000000000000000000000000000000000000010000000000000000000000000,
|
INIT_LMR = 66'b000000000000000000000000000000000000000100000000000000000000000000,
|
INIT_LMR = 66'b000000000000000000000000000000000000000100000000000000000000000000,
|
SUSP1 = 66'b000000000000000000000000000000000000001000000000000000000000000000,
|
SUSP1 = 66'b000000000000000000000000000000000000001000000000000000000000000000,
|
SUSP2 = 66'b000000000000000000000000000000000000010000000000000000000000000000,
|
SUSP2 = 66'b000000000000000000000000000000000000010000000000000000000000000000,
|
SUSP3 = 66'b000000000000000000000000000000000000100000000000000000000000000000,
|
SUSP3 = 66'b000000000000000000000000000000000000100000000000000000000000000000,
|
| Line 299... |
Line 299... |
wire kro;
|
wire kro;
|
|
|
wire cs_a;
|
wire cs_a;
|
reg [3:0] cmd;
|
reg [3:0] cmd;
|
|
|
reg mem_ack;
|
wire mem_ack;
|
wire mem_ack_s;
|
wire mem_ack_s;
|
reg mem_ack_d;
|
reg mem_ack_d;
|
reg err_d;
|
reg err_d;
|
reg err;
|
wire err;
|
reg cmd_a10;
|
reg cmd_a10;
|
reg lmr_ack;
|
reg lmr_ack;
|
reg row_sel;
|
reg row_sel;
|
reg oe_;
|
reg oe_;
|
reg oe_d;
|
reg oe_d;
|
| Line 335... |
Line 335... |
reg [10:0] burst_cnt;
|
reg [10:0] burst_cnt;
|
wire burst_act;
|
wire burst_act;
|
reg burst_act_rd;
|
reg burst_act_rd;
|
wire single_write;
|
wire single_write;
|
|
|
|
reg cs_le_d;
|
reg cs_le;
|
reg cs_le;
|
|
reg cs_le_r;
|
|
|
reg susp_req_r;
|
reg susp_req_r;
|
reg resume_req_r;
|
reg resume_req_r;
|
reg suspended;
|
reg suspended;
|
reg suspended_d;
|
reg suspended_d;
|
//wire susp_sel;
|
|
reg susp_sel_set, susp_sel_clr, susp_sel_r;
|
reg susp_sel_set, susp_sel_clr, susp_sel_r;
|
|
|
reg [3:0] cmd_del;
|
reg [3:0] cmd_del;
|
reg [3:0] cmd_r;
|
reg [3:0] cmd_r;
|
reg data_oe_r;
|
reg data_oe_r;
|
| Line 394... |
Line 395... |
|
|
reg mc_c_oe_d;
|
reg mc_c_oe_d;
|
reg mc_c_oe;
|
reg mc_c_oe;
|
|
|
reg mc_le;
|
reg mc_le;
|
|
reg mem_ack_r;
|
|
|
|
reg rsts, rsts1;
|
|
reg no_wb_cycle;
|
|
|
|
wire bc_dec;
|
|
reg ap_en; // Auto Precharge Enable
|
|
reg cmd_a10_r;
|
|
reg wb_stb_first;
|
|
reg tmr_ld_tavav;
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Aliases
|
// Aliases
|
//
|
//
|
assign mem_type = csc[3:1];
|
assign mem_type = csc[3:1];
|
assign bus_width = csc[5:4];
|
assign bus_width = csc[5:4];
|
assign kro = csc[10];
|
assign kro = csc[10];
|
assign single_write = tms[9];
|
assign single_write = tms[9] | (tms[2:0] == 3'h0);
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Misc Logic
|
// Misc Logic
|
//
|
//
|
|
reg cs_le_r1;
|
|
|
|
always @(posedge clk)
|
|
cs_le_r <= #1 cs_le_r1;
|
|
|
|
always @(posedge clk)
|
|
cs_le_r1 <= #1 cs_le;
|
|
|
|
always @(posedge clk)
|
|
cs_le <= #1 cs_le_d;
|
|
|
reg rsts, rsts1;
|
|
always @(posedge mc_clk)
|
always @(posedge mc_clk)
|
rsts1 <= #1 rst;
|
rsts1 <= #1 rst;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
rsts <= #1 rsts1;
|
rsts <= #1 rsts1;
|
| Line 448... |
Line 468... |
|
|
// Any Chip Select
|
// Any Chip Select
|
assign cs_a = |cs;
|
assign cs_a = |cs;
|
|
|
// Memory to Wishbone Ack
|
// Memory to Wishbone Ack
|
always @(posedge clk)
|
assign mem_ack = (mem_ack_d | mem_ack_s) & (wb_read_go | wb_write_go);
|
mem_ack <= #1 (mem_ack_d | mem_ack_s) & (wb_read_go | wb_write_go);
|
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
err <= #1 err_d;
|
mem_ack_r <= #1 mem_ack;
|
|
|
|
assign err = err_d;
|
|
|
// SDRAM Command, either delayed (for writes) or straight through
|
// SDRAM Command, either delayed (for writes) or straight through
|
always @(posedge clk)
|
always @(posedge clk)
|
cmd_r <= #1 cmd;
|
cmd_r <= #1 cmd;
|
|
|
| Line 510... |
Line 531... |
always @(posedge clk)
|
always @(posedge clk)
|
wb_wait_r <= #1 wb_wait_r2;
|
wb_wait_r <= #1 wb_wait_r2;
|
|
|
// Indicates when the row_same and bank_open lookups are done
|
// Indicates when the row_same and bank_open lookups are done
|
always @(posedge clk)
|
always @(posedge clk)
|
lookup_ready1 <= #1 cs_le;
|
lookup_ready1 <= #1 cs_le & wb_stb_i;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
lookup_ready2 <= #1 lookup_ready1;
|
lookup_ready2 <= #1 lookup_ready1 & wb_stb_i;
|
|
|
// Keep Track if it is a SDRAM write cycle
|
// Keep Track if it is a SDRAM write cycle
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if(rst) wr_cycle <= #1 1'b0;
|
if(rst) wr_cycle <= #1 1'b0;
|
else
|
else
|
| Line 531... |
Line 552... |
else
|
else
|
if(wb_cycle_set) wb_cycle <= #1 1'b1;
|
if(wb_cycle_set) wb_cycle <= #1 1'b1;
|
else
|
else
|
if(!wb_cyc_i) wb_cycle <= #1 1'b0;
|
if(!wb_cyc_i) wb_cycle <= #1 1'b0;
|
|
|
|
// Thses two signals are used to signal that no wishbone cycle is in
|
|
// progress. Need to register them to avoid a very long combinatorial
|
|
// path ....
|
|
always @(posedge clk)
|
|
no_wb_cycle <= #1 !wb_read_go & !wb_write_go;
|
|
|
// Track ack's for read cycles
|
// Track ack's for read cycles
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if(rst) ack_cnt <= #1 4'h0;
|
if(rst) ack_cnt <= #1 4'h0;
|
else
|
else
|
if(!wb_read_go & !wb_write_go) ack_cnt <= #1 4'h0;
|
if(no_wb_cycle) ack_cnt <= #1 4'h0;
|
else
|
else
|
if(dv & !mem_ack_s) ack_cnt <= #1 ack_cnt + 4'h1;
|
if(dv & !mem_ack_s) ack_cnt <= #1 ack_cnt + 4'h1;
|
else
|
else
|
if(!dv & mem_ack_s) ack_cnt <= #1 ack_cnt - 4'h1;
|
if(!dv & mem_ack_s) ack_cnt <= #1 ack_cnt - 4'h1;
|
|
|
assign ack_cnt_is_0 = (ack_cnt==4'h0);
|
assign ack_cnt_is_0 = (ack_cnt==4'h0);
|
|
|
assign mem_ack_s = (ack_cnt != 4'h0) & !wb_wait & !mem_ack & wb_read_go & !(wb_we_i & wb_stb_i);
|
assign mem_ack_s = (ack_cnt != 4'h0) & !wb_wait & !mem_ack_r & wb_read_go & !(wb_we_i & wb_stb_i);
|
|
|
// Internal Cycle Tracker
|
// Internal Cycle Tracker
|
always @(posedge clk)
|
always @(posedge clk)
|
cnt <= #1 cnt_next;
|
cnt <= #1 cnt_next;
|
|
|
| Line 576... |
Line 603... |
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Timing Logic
|
// Timing Logic
|
//
|
//
|
|
wire [3:0] twrp;
|
|
wire twd_is_zero;
|
wire [31:0] tms_x;
|
wire [31:0] tms_x;
|
|
|
// FIX_ME
|
// FIX_ME
|
|
// Hard wire worst case or make it programmable ???
|
assign tms_x = (rfr_ack | rfr_ack_r | susp_sel | !mc_c_oe) ? 32'hffff_ffff : tms;
|
assign tms_x = (rfr_ack | rfr_ack_r | susp_sel | !mc_c_oe) ? 32'hffff_ffff : tms;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if(tmr2_ld_tscsto) timer2 <= #1 tms_x[24:16];
|
if(tmr2_ld_tscsto) timer2 <= #1 tms_x[24:16];
|
else
|
else
|
if(tmr2_ld_tsrdv) timer2 <= #1 9'd2; // SSRAM RD->1st DATA VALID
|
if(tmr2_ld_tsrdv) timer2 <= #1 9'd4; // SSRAM RD->1st DATA VALID
|
else
|
else
|
if(tmr2_ld_twpw) timer2 <= #1 { 5'h0, tms_x[15:12]};
|
if(tmr2_ld_twpw) timer2 <= #1 { 5'h0, tms_x[15:12]};
|
else
|
else
|
if(tmr2_ld_twd) timer2 <= #1 { 4'h0, tms_x[19:16],1'b0};
|
if(tmr2_ld_twd) timer2 <= #1 { 4'h0, tms_x[19:16],1'b0};
|
else
|
else
|
| Line 598... |
Line 628... |
else
|
else
|
if(tmr2_ld_trdv) timer2 <= #1 { tms_x[7:0], 1'b1};
|
if(tmr2_ld_trdv) timer2 <= #1 { tms_x[7:0], 1'b1};
|
else
|
else
|
if(!timer2_is_zero) timer2 <= #1 timer2 - 9'b1;
|
if(!timer2_is_zero) timer2 <= #1 timer2 - 9'b1;
|
|
|
wire twd_is_zero;
|
|
assign twd_is_zero = (tms_x[19:16] == 4'h0);
|
assign twd_is_zero = (tms_x[19:16] == 4'h0);
|
|
|
assign timer2_is_zero = (timer2 == 9'h0);
|
assign timer2_is_zero = (timer2 == 9'h0);
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
tmr2_done <= #1 timer2_is_zero & !tmr2_ld_trdv & !tmr2_ld_trdz &
|
tmr2_done <= #1 timer2_is_zero & !tmr2_ld_trdv & !tmr2_ld_trdz &
|
!tmr2_ld_twpw & !tmr2_ld_twd & !tmr2_ld_twwd & !tmr2_ld_tscsto;
|
!tmr2_ld_twpw & !tmr2_ld_twd & !tmr2_ld_twwd & !tmr2_ld_tscsto;
|
|
|
wire [3:0] twrp;
|
assign twrp = {2'h0,tms_x[16:15]} + tms_x[23:20];
|
|
|
assign twrp = tms_x[16:15] + tms_x[23:20];
|
|
|
|
// SDRAM Memories timing tracker
|
// SDRAM Memories timing tracker
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
`ifdef MC_POR_DELAY
|
`ifdef MC_POR_DELAY
|
if(rst) timer <= #1 `MC_POR_DELAY_VAL ;
|
if(rst) timer <= #1 `MC_POR_DELAY_VAL ;
|
| Line 623... |
Line 650... |
else
|
else
|
if(tmr_ld_trdz) timer <= #1 { 4'h0, tms_x[11:8] };
|
if(tmr_ld_trdz) timer <= #1 { 4'h0, tms_x[11:8] };
|
else
|
else
|
if(tmr_ld_trdv) timer <= #1 tms_x[7:0];
|
if(tmr_ld_trdv) timer <= #1 tms_x[7:0];
|
else
|
else
|
//if(tmr_ld_twr) timer <= #1 { 6'h0, tms_x[16:15]};
|
|
if(tmr_ld_twr) timer <= #1 { 4'h0, twrp};
|
if(tmr_ld_twr) timer <= #1 { 4'h0, twrp};
|
else
|
else
|
if(tmr_ld_trp) timer <= #1 { 4'h0, tms_x[23:20]};
|
if(tmr_ld_trp) timer <= #1 { 4'h0, tms_x[23:20]};
|
else
|
else
|
if(tmr_ld_trcd) timer <= #1 { 5'h0, tms_x[19:17]};
|
if(tmr_ld_trcd) timer <= #1 { 5'h0, tms_x[19:17]};
|
else
|
else
|
if(tmr_ld_tcl) timer <= #1 { 6'h0, tms_x[05:04]};
|
if(tmr_ld_tcl) timer <= #1 { 6'h0, tms_x[05:04]};
|
else
|
else
|
if(tmr_ld_trfc) timer <= #1 { 4'h0, tms_x[27:24]};
|
if(tmr_ld_trfc) timer <= #1 { 4'h0, tms_x[27:24]};
|
else
|
else
|
if(tmr_ld_txsr) timer <= #1 8'd7;
|
if(tmr_ld_tavav) timer <= #1 8'h3;
|
|
else
|
|
if(tmr_ld_txsr) timer <= #1 8'h7;
|
else
|
else
|
if(!timer_is_zero & !mc_le) timer <= #1 timer - 8'b1;
|
if(!timer_is_zero & !mc_le) timer <= #1 timer - 8'b1;
|
|
|
assign timer_is_zero = (timer == 8'h0);
|
assign timer_is_zero = (timer == 8'h0);
|
|
|
| Line 655... |
Line 683... |
ir_cnt_done <= #1 (ir_cnt == 4'h0);
|
ir_cnt_done <= #1 (ir_cnt == 4'h0);
|
|
|
// Burst Counter
|
// Burst Counter
|
always @(tms_x or page_size)
|
always @(tms_x or page_size)
|
case(tms_x[2:0]) // synopsys full_case parallel_case
|
case(tms_x[2:0]) // synopsys full_case parallel_case
|
3'h0: burst_val = 11'd1;
|
3'h0: burst_val = 11'h1;
|
3'h1: burst_val = 11'd2;
|
3'h1: burst_val = 11'h2;
|
3'h2: burst_val = 11'd4;
|
3'h2: burst_val = 11'h4;
|
3'h3: burst_val = 11'd8;
|
3'h3: burst_val = 11'h8;
|
3'h7: burst_val = page_size;
|
3'h7: burst_val = page_size;
|
endcase
|
endcase
|
|
|
|
assign bc_dec = wr_cycle ? mem_ack_d : dv;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if(burst_cnt_ld_4) burst_cnt <= #1 11'h4;
|
if(burst_cnt_ld_4) burst_cnt <= #1 11'h4; // for SSRAM only
|
else
|
else
|
if(burst_cnt_ld) burst_cnt <= #1 burst_val;
|
if(burst_cnt_ld) burst_cnt <= #1 burst_val;
|
else
|
else
|
if(wr_cycle ? mem_ack_d : dv) burst_cnt <= #1 burst_cnt - 11'h1;
|
if(bc_dec) burst_cnt <= #1 burst_cnt - 11'h1;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
if(burst_cnt_ld) burst_fp <= #1 (tms_x[2:0] == 3'h7);
|
if(burst_cnt_ld) burst_fp <= #1 (tms_x[2:0] == 3'h7);
|
|
|
|
// Auto Precharge Enable
|
|
always @(posedge clk)
|
|
if(burst_cnt_ld) ap_en <= #1 (tms_x[2:0] == 3'h0) & !kro;
|
|
|
assign burst_act = |burst_cnt & ( |tms_x[2:0] );
|
assign burst_act = |burst_cnt & ( |tms_x[2:0] );
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
burst_act_rd <= #1 |burst_cnt;
|
burst_act_rd <= #1 |burst_cnt;
|
|
|
always @(posedge clk)
|
always @(posedge clk)
|
dv_r <= #1 dv;
|
dv_r <= #1 dv;
|
|
|
|
always @(posedge clk) // Auto Precharge Holding Register
|
|
cmd_a10_r <= #1 cmd_a10;
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Main State Machine
|
// Main State Machine
|
//
|
//
|
|
reg wb_write_go_r;
|
|
|
|
always @(posedge clk)
|
|
wb_write_go_r <= #1 wb_write_go;
|
|
|
|
|
|
always @(posedge clk or posedge rst)
|
|
if(rst) wb_stb_first <= #1 1'b0;
|
|
else
|
|
if(mem_ack) wb_stb_first <= #1 1'b0;
|
|
else
|
|
if(wb_first & wb_stb_i) wb_stb_first <= #1 1'b1;
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
`ifdef MC_POR_DELAY
|
`ifdef MC_POR_DELAY
|
if(rst) state <= #1 POR;
|
if(rst) state <= #1 POR;
|
`else
|
`else
|
if(rst) state <= #1 IDLE;
|
if(rst) state <= #1 IDLE;
|
`endif
|
`endif
|
else state <= #1 next_state;
|
else state <= #1 next_state;
|
|
|
always @(state or cs_a or
|
always @(state or cs_a or cs_le or cs_le_r or
|
twd_is_zero or wb_stb_i or
|
twd_is_zero or wb_stb_i or wb_write_go_r or
|
wb_first or wb_read_go or wb_write_go or wb_wait or mem_ack or wb_we_i or
|
wb_first or wb_read_go or wb_write_go or wb_wait or mem_ack_r or wb_we_i or
|
ack_cnt_is_0 or wb_wait_r or cnt or wb_cycle or
|
ack_cnt_is_0 or wb_wait_r or cnt or wb_cycle or wr_cycle or
|
mem_type or kro or lookup_ready1 or lookup_ready2 or row_same or
|
mem_type or kro or lookup_ready2 or row_same or cmd_a10_r or
|
bank_open or single_write or
|
bank_open or single_write or
|
cmd_asserted or tmr_done or tmr2_done or ir_cnt_done or cmd_asserted2 or
|
cmd_asserted or tmr_done or tmr2_done or ir_cnt_done or cmd_asserted2 or
|
burst_act or burst_act_rd or burst_fp or cke_ or cke_r or cke_o_del or
|
burst_act or burst_act_rd or burst_fp or cke_ or cke_r or cke_o_del or
|
rfr_req or lmr_req or init_req or rfr_ack_r or susp_req_r or resume_req_r or
|
rfr_req or lmr_req or init_req or rfr_ack_r or susp_req_r or resume_req_r or
|
mc_br or bw8 or bw16 or dv_r or mc_adv_r or mc_ack
|
mc_br or bw8 or bw16 or dv_r or mc_adv_r or mc_ack or wb_stb_first or ap_en
|
)
|
)
|
begin
|
begin
|
next_state = state; // Default keep current state
|
next_state = state; // Default keep current state
|
cnt_next = 1'b0;
|
cnt_next = 1'b0;
|
|
|
cmd = `MC_CMD_NOP;
|
cmd = `MC_CMD_NOP;
|
cmd_a10 = ~kro;
|
cmd_a10 = ap_en;
|
oe_d = 1'b0;
|
oe_d = 1'b0;
|
data_oe_d = 1'b0;
|
data_oe_d = 1'b0;
|
cke_d = 1'b1;
|
cke_d = 1'b1;
|
cke_rd = 1'b1;
|
cke_rd = 1'b1;
|
mc_adsc = 1'b0;
|
mc_adsc = 1'b0;
|
| Line 732... |
Line 781... |
tmr_ld_twr = 1'b0;
|
tmr_ld_twr = 1'b0;
|
tmr_ld_txsr = 1'b0;
|
tmr_ld_txsr = 1'b0;
|
tmr_ld_trdv = 1'b0;
|
tmr_ld_trdv = 1'b0;
|
tmr_ld_trdz = 1'b0;
|
tmr_ld_trdz = 1'b0;
|
tmr_ld_twr2 = 1'b0;
|
tmr_ld_twr2 = 1'b0;
|
|
tmr_ld_tavav = 1'b0;
|
|
|
tmr2_ld_trdv = 1'b0;
|
tmr2_ld_trdv = 1'b0;
|
tmr2_ld_trdz = 1'b0;
|
tmr2_ld_trdz = 1'b0;
|
|
|
tmr2_ld_twpw = 1'b0;
|
tmr2_ld_twpw = 1'b0;
|
| Line 752... |
Line 802... |
|
|
ir_cnt_dec = 1'b0;
|
ir_cnt_dec = 1'b0;
|
ir_cnt_ld = 1'b0;
|
ir_cnt_ld = 1'b0;
|
|
|
row_sel = 1'b0;
|
row_sel = 1'b0;
|
cs_le = 1'b0;
|
cs_le_d = 1'b0;
|
wr_clr = 1'b0;
|
wr_clr = 1'b0;
|
wr_set = 1'b0;
|
wr_set = 1'b0;
|
wb_cycle_set = 1'b0;
|
wb_cycle_set = 1'b0;
|
dv = 1'b0;
|
dv = 1'b0;
|
|
|
| Line 779... |
Line 829... |
if(tmr_done) next_state = IDLE;
|
if(tmr_done) next_state = IDLE;
|
end
|
end
|
`endif
|
`endif
|
IDLE:
|
IDLE:
|
begin
|
begin
|
cs_le = (wb_first & wb_stb_i) | lmr_req;
|
cs_le_d = wb_stb_first | lmr_req;
|
burst_cnt_ld = 1'b1;
|
burst_cnt_ld = 1'b1;
|
wr_clr = 1'b1;
|
wr_clr = 1'b1;
|
|
|
|
if(mem_type == `MC_MEM_TYPE_SCS) tmr2_ld_tscsto = 1'b1;
|
|
if(mem_type == `MC_MEM_TYPE_SRAM) tmr2_ld_tsrdv = 1'b1;
|
|
|
|
|
if(rfr_req)
|
if(rfr_req)
|
begin
|
begin
|
rfr_ack = 1'b1;
|
rfr_ack = 1'b1;
|
next_state = PRECHARGE;
|
next_state = PRECHARGE;
|
end
|
end
|
else
|
else
|
if(init_req)
|
if(init_req)
|
begin
|
begin
|
cs_le = 1'b1;
|
cs_le_d = 1'b1;
|
next_state = INIT0;
|
next_state = INIT0;
|
end
|
end
|
else
|
else
|
if(lmr_req & lookup_ready2)
|
if(lmr_req & lookup_ready2)
|
begin
|
begin
|
lmr_ack = 1'b1;
|
lmr_ack = 1'b1;
|
cs_le = 1'b1;
|
cs_le_d = 1'b1;
|
next_state = LMR0;
|
next_state = LMR0;
|
end
|
end
|
else
|
else
|
if(susp_req_r & !wb_cycle)
|
if(susp_req_r & !wb_cycle)
|
begin
|
begin
|
cs_le = 1'b1;
|
cs_le_d = 1'b1;
|
susp_sel_set = 1'b1;
|
susp_sel_set = 1'b1;
|
next_state = SUSP1;
|
next_state = SUSP1;
|
end
|
end
|
else
|
else
|
if(cs_a & (wb_read_go | wb_write_go) & (lookup_ready1 | wb_cycle) )
|
if(cs_a & (wb_read_go | wb_write_go) & lookup_ready2)
|
begin
|
begin
|
wb_cycle_set = 1'b1;
|
wb_cycle_set = 1'b1;
|
case(mem_type) // synopsys full_case parallel_case
|
case(mem_type) // synopsys full_case parallel_case
|
`MC_MEM_TYPE_SDRAM: // SDRAM
|
`MC_MEM_TYPE_SDRAM: // SDRAM
|
if((lookup_ready2 | wb_cycle) & !wb_wait)
|
if((lookup_ready2) & !wb_wait)
|
begin
|
begin
|
if(wb_write_go | (wb_we_i & wb_stb_i)) wr_set = 1'b1;
|
if(wb_write_go | (wb_we_i & wb_stb_i)) wr_set = 1'b1;
|
if(kro & bank_open & row_same) next_state = SD_RD_WR;
|
if(kro & bank_open & row_same) next_state = SD_RD_WR;
|
else
|
else
|
if(kro & bank_open) next_state = PRECHARGE;
|
if(kro & bank_open) next_state = PRECHARGE;
|
| Line 826... |
Line 880... |
end
|
end
|
`MC_MEM_TYPE_ACS:
|
`MC_MEM_TYPE_ACS:
|
begin // Async Chip Select
|
begin // Async Chip Select
|
if(!wb_wait)
|
if(!wb_wait)
|
begin
|
begin
|
cs_le = 1'b1;
|
cs_le_d = 1'b1;
|
if(wb_write_go)
|
if(wb_write_go)
|
begin
|
begin
|
data_oe_d = 1'b1;
|
data_oe_d = 1'b1;
|
next_state = ACS_WR;
|
next_state = ACS_WR;
|
end
|
end
|
| Line 839... |
Line 893... |
end
|
end
|
`MC_MEM_TYPE_SCS:
|
`MC_MEM_TYPE_SCS:
|
begin // Sync Chip Select
|
begin // Sync Chip Select
|
if(!wb_wait)
|
if(!wb_wait)
|
begin
|
begin
|
tmr2_ld_tscsto = 1'b1;
|
cs_le_d = 1'b1;
|
cs_le = 1'b1;
|
|
if(wb_write_go)
|
if(wb_write_go)
|
begin
|
begin
|
cmd = `MC_CMD_XWR;
|
cmd = `MC_CMD_XWR;
|
data_oe_d = 1'b1;
|
data_oe_d = 1'b1;
|
tmr_ld_twr2 = 1'b1;
|
tmr_ld_twr2 = 1'b1;
|
| Line 861... |
Line 914... |
end
|
end
|
`MC_MEM_TYPE_SRAM:
|
`MC_MEM_TYPE_SRAM:
|
begin // SRAM
|
begin // SRAM
|
if(!wb_wait)
|
if(!wb_wait)
|
begin
|
begin
|
cs_le = 1'b1;
|
cs_le_d = 1'b1;
|
if(wb_write_go)
|
if(wb_write_go)
|
begin
|
begin
|
data_oe_d = 1'b1;
|
data_oe_d = 1'b1;
|
mem_ack_d = 1'b1;
|
mem_ack_d = 1'b1;
|
next_state = SRAM_WR;
|
next_state = SRAM_WR;
|
| Line 873... |
Line 926... |
else
|
else
|
begin
|
begin
|
cmd = `MC_CMD_XRD;
|
cmd = `MC_CMD_XRD;
|
oe_d = 1'b1;
|
oe_d = 1'b1;
|
mc_adsc = 1'b1;
|
mc_adsc = 1'b1;
|
tmr2_ld_tsrdv = 1'b1;
|
|
next_state = SRAM_RD;
|
next_state = SRAM_RD;
|
end
|
end
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
else
|
else
|
if(mc_br)
|
if(mc_br)
|
begin
|
begin
|
if(!cmd_asserted2) next_state = BG0;
|
if(!cmd_asserted2)
|
|
begin
|
|
next_state = BG0;
|
|
mc_c_oe_d = 1'b0;
|
|
end
|
end
|
end
|
end
|
end
|
|
|
IDLE_T:
|
IDLE_T:
|
begin
|
begin
|
cs_le = (wb_first & wb_stb_i) | lmr_req;
|
cmd_a10 = cmd_a10_r; // Hold Auto Precharge 'til cycle finishes
|
|
if(tmr_done & wb_cycle & !wb_wait) cs_le_d = 1'b1;
|
if(tmr_done) next_state = IDLE;
|
if(tmr_done) next_state = IDLE;
|
end
|
end
|
|
|
IDLE_T2:
|
IDLE_T2:
|
begin
|
begin
|
if(tmr2_done) next_state = IDLE;
|
if(tmr2_done & (!wb_wait | !wb_cycle) )
|
|
begin
|
|
cs_le_d = 1'b1;
|
|
if(cs_le_r) next_state = IDLE;
|
|
end
|
end
|
end
|
|
|
/////////////////////////////////////////
|
/////////////////////////////////////////
|
// SCS STATES ....
|
// SCS STATES ....
|
/////////////////////////////////////////
|
/////////////////////////////////////////
|
| Line 960... |
Line 1021... |
end
|
end
|
|
|
/////////////////////////////////////////
|
/////////////////////////////////////////
|
// SSRAM STATES ....
|
// SSRAM STATES ....
|
/////////////////////////////////////////
|
/////////////////////////////////////////
|
|
|
SRAM_RD:
|
SRAM_RD:
|
begin
|
begin
|
cmd = `MC_CMD_XRD;
|
cmd = `MC_CMD_XRD;
|
oe_d = 1'b1;
|
oe_d = 1'b1;
|
mc_adsc = 1'b1;
|
mc_adsc = 1'b1;
|
| Line 1012... |
Line 1072... |
next_state = SRAM_RD4;
|
next_state = SRAM_RD4;
|
end
|
end
|
else
|
else
|
if(!wb_wait)
|
if(!wb_wait)
|
begin
|
begin
|
cs_le = 1'b1;
|
cs_le_d = 1'b1;
|
next_state = SRAM_RD;
|
next_state = SRAM_RD;
|
end
|
end
|
end
|
end
|
|
|
SRAM_RD4: // DESELECT
|
SRAM_RD4: // DESELECT
|
begin
|
begin
|
mc_adsc = 1'b1;
|
mc_adsc = 1'b1;
|
next_state = IDLE;
|
next_state = IDLE;
|
end
|
end
|
|
|
SRAM_WR: // 80
|
SRAM_WR:
|
begin
|
begin
|
cmd = `MC_CMD_XWR;
|
cmd = `MC_CMD_XWR;
|
mc_adsc = 1'b1;
|
mc_adsc = 1'b1;
|
data_oe_d = 1'b1;
|
data_oe_d = 1'b1;
|
if(cmd_asserted)
|
if(cmd_asserted)
|
| Line 1040... |
Line 1100... |
next_state = SRAM_RD4;
|
next_state = SRAM_RD4;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
data_oe_d = 1'b1;
|
data_oe_d = 1'b1;
|
mem_ack_d = ~mem_ack;
|
mem_ack_d = ~mem_ack_r;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
SRAM_WR0: // 81
|
SRAM_WR0:
|
begin
|
begin
|
if(wb_wait) next_state = SRAM_WR0;
|
if(wb_wait) next_state = SRAM_WR0;
|
else
|
else
|
if(!wb_write_go)
|
if(!wb_write_go)
|
begin
|
begin
|
| Line 1057... |
Line 1117... |
next_state = SRAM_RD4;
|
next_state = SRAM_RD4;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
data_oe_d = 1'b1;
|
data_oe_d = 1'b1;
|
//mem_ack_d = ~mem_ack;
|
|
next_state = SRAM_WR;
|
next_state = SRAM_WR;
|
end
|
end
|
|
|
//data_oe_d = 1'b1;
|
|
//if(!wb_wait) next_state = SRAM_WR;
|
|
end
|
end
|
|
|
/////////////////////////////////////////
|
/////////////////////////////////////////
|
// Async Devices STATES ....
|
// Async Devices STATES ....
|
/////////////////////////////////////////
|
/////////////////////////////////////////
|
| Line 1087... |
Line 1143... |
if(bw8 | bw16) next_adr = 1'b1;
|
if(bw8 | bw16) next_adr = 1'b1;
|
if(bw8) next_state = ACS_RD_8_1;
|
if(bw8) next_state = ACS_RD_8_1;
|
else
|
else
|
if(bw16) next_state = ACS_RD_8_5;
|
if(bw16) next_state = ACS_RD_8_5;
|
else next_state = ACS_RD2A;
|
else next_state = ACS_RD2A;
|
//else next_state = ACS_RD3;
|
|
end
|
end
|
end
|
end
|
|
|
ACS_RD_8_1:
|
ACS_RD_8_1:
|
begin // 8 bit 2nd byte
|
begin // 8 bit 2nd byte
|
| Line 1247... |
Line 1302... |
if(rfr_ack_r) next_state = REFR;
|
if(rfr_ack_r) next_state = REFR;
|
else next_state = ACTIVATE;
|
else next_state = ACTIVATE;
|
end
|
end
|
end
|
end
|
|
|
ACTIVATE: // 4
|
ACTIVATE:
|
begin
|
begin
|
if(!wb_wait_r)
|
if(!wb_wait_r)
|
begin
|
begin
|
row_sel = 1'b1;
|
row_sel = 1'b1;
|
tmr_ld_trcd = 1'b1;
|
tmr_ld_trcd = 1'b1;
|
| Line 1269... |
Line 1324... |
|
|
if(tmr_done)
|
if(tmr_done)
|
begin
|
begin
|
if(wb_write_go)
|
if(wb_write_go)
|
begin
|
begin
|
mem_ack_d = !mem_ack;
|
mem_ack_d = ~mem_ack_r;
|
cmd_a10 = ~kro;
|
cmd_a10 = ap_en | (single_write & !kro);
|
next_state = SD_WR;
|
next_state = SD_WR;
|
end
|
end
|
else
|
else
|
if(!wb_wait_r) next_state = SD_RD;
|
if(!wb_wait_r) next_state = SD_RD;
|
end
|
end
|
end
|
end
|
|
|
SD_RD_WR: // 6
|
SD_RD_WR:
|
begin
|
begin
|
if(wb_write_go | (wb_we_i & wb_stb_i)) wr_set = 1'b1;
|
if(wb_write_go | (wb_we_i & wb_stb_i)) wr_set = 1'b1;
|
|
|
if(wb_write_go & !wb_wait)
|
if(wb_write_go & !wb_wait)
|
begin // Write
|
begin // Write
|
data_oe_d = 1'b1;
|
data_oe_d = 1'b1;
|
mem_ack_d = !mem_ack;
|
mem_ack_d = ~mem_ack_r;
|
cmd_a10 = ~kro;
|
cmd_a10 = ap_en | (single_write & !kro);
|
next_state = SD_WR;
|
next_state = SD_WR;
|
end
|
end
|
else
|
else
|
if(!wb_wait)
|
if(!wb_wait)
|
begin // Read
|
begin // Read
|
| Line 1300... |
Line 1355... |
end
|
end
|
else next_state = SD_RD;
|
else next_state = SD_RD;
|
end
|
end
|
end
|
end
|
|
|
SD_WR: // Write Command A
|
SD_WR: // Write Command
|
begin // Does the first single write
|
begin // Does the first single write
|
data_oe_d = 1'b1;
|
data_oe_d = 1'b1;
|
tmr_ld_twr = 1'b1;
|
tmr_ld_twr = 1'b1;
|
cnt_next = ~cnt;
|
cnt_next = ~cnt;
|
cmd = `MC_CMD_WR;
|
cmd = `MC_CMD_WR;
|
cmd_a10 = ~kro;
|
|
|
|
if(!cnt & wb_cycle & burst_act) cke_d = !wb_wait;
|
cmd_a10 = ap_en | (single_write & !kro);
|
|
|
|
if(!cnt & wb_cycle & burst_act) cke_d = ~wb_wait;
|
else cke_d = cke_r;
|
else cke_d = cke_r;
|
|
|
if(cmd_asserted)
|
if(cmd_asserted)
|
begin
|
begin
|
mem_ack_d = !mem_ack & wb_write_go & !wb_wait & wb_cycle & burst_act;
|
mem_ack_d = !mem_ack_r & wb_write_go & !wb_wait & wb_cycle & burst_act;
|
|
|
if(wb_cycle & !burst_act) next_state = IDLE_T;
|
if(wb_cycle & !burst_act) next_state = IDLE_T;
|
else
|
else
|
if(wb_cycle) next_state = SD_WR_W;
|
if(wb_write_go) next_state = SD_WR_W;
|
else
|
else
|
if(burst_act & !single_write) next_state = BT;
|
if(burst_act & !single_write) next_state = BT;
|
|
else
|
|
if(!ap_en) next_state = BT_W;
|
else next_state = IDLE_T;
|
else next_state = IDLE_T;
|
end
|
end
|
|
|
end
|
end
|
|
|
SD_WR_W: // B
|
SD_WR_W:
|
begin // Does additional Writes or Times them
|
begin // Does additional Writes or Times them
|
tmr_ld_twr = 1'b1;
|
tmr_ld_twr = 1'b1;
|
cnt_next = ~cnt;
|
cnt_next = ~cnt;
|
|
|
if(single_write & wb_cycle)
|
if(single_write & wb_cycle)
|
begin
|
begin
|
cmd = `MC_CMD_WR;
|
cmd = `MC_CMD_WR;
|
if(burst_act) cmd_a10 = 1'b0;
|
|
else cmd_a10 = ~kro;
|
|
end
|
end
|
|
cmd_a10 = ap_en | (single_write & !kro);
|
|
|
data_oe_d = 1'b1;
|
data_oe_d = 1'b1;
|
mem_ack_d = !mem_ack & wb_write_go & !wb_wait & wb_cycle & burst_act;
|
mem_ack_d = !mem_ack_r & wb_write_go & !wb_wait & wr_cycle & burst_act;
|
|
|
if(!cnt) cke_d = ~wb_wait;
|
if(!cnt) cke_d = ~wb_wait;
|
else cke_d = cke_r;
|
else cke_d = cke_r;
|
|
|
if(cke_r)
|
if( (single_write & cke_r) | (!single_write & !cnt & !wb_wait) | (!single_write & cnt & cke_r) )
|
begin
|
begin
|
if(single_write & !wb_cycle) next_state = IDLE_T;
|
if(single_write & !wb_cycle) next_state = IDLE_T;
|
else
|
else
|
if(burst_act & !single_write & !wb_write_go )
|
if(burst_act & !single_write & !wb_write_go_r)
|
|
begin
|
|
cmd = `MC_CMD_BT;
|
next_state = BT;
|
next_state = BT;
|
|
end
|
|
else
|
|
if(!burst_act & !ap_en) next_state = BT_W;
|
else
|
else
|
if(!burst_act) next_state = IDLE_T;
|
if(!burst_act) next_state = IDLE_T;
|
else
|
else
|
if(!wb_write_go & wb_read_go) next_state = IDLE_T; // Added for WMR
|
if(!wb_write_go_r & wb_read_go) next_state = IDLE_T; // Added for WMR
|
end
|
end
|
end
|
end
|
|
|
SD_RD: // Read Command 7
|
SD_RD: // Read Command
|
begin
|
begin
|
cmd = `MC_CMD_RD;
|
cmd = `MC_CMD_RD;
|
if(burst_fp) cmd_a10 = 1'b0;
|
cmd_a10 = ap_en;
|
else cmd_a10 = ~kro;
|
|
tmr_ld_tcl = 1'b1;
|
tmr_ld_tcl = 1'b1;
|
if(cmd_asserted) next_state = SD_RD_W;
|
if(cmd_asserted) next_state = SD_RD_W;
|
end
|
end
|
|
|
SD_RD_W: // 8
|
SD_RD_W:
|
begin
|
begin
|
if(tmr_done) next_state = SD_RD_LOOP;
|
if(tmr_done) next_state = SD_RD_LOOP;
|
end
|
end
|
|
|
SD_RD_LOOP: // 9
|
SD_RD_LOOP:
|
begin
|
begin
|
|
|
cnt_next = ~cnt;
|
cnt_next = ~cnt;
|
|
|
if(cnt & !(burst_act & !wb_cycle) & burst_act ) cke_rd = !wb_wait;
|
if(cnt & !(burst_act & !wb_cycle) & burst_act ) cke_rd = !wb_wait;
|
else cke_rd = cke_;
|
else cke_rd = cke_;
|
|
|
| Line 1387... |
Line 1447... |
if(burst_act & !wb_cycle) next_state = BT;
|
if(burst_act & !wb_cycle) next_state = BT;
|
else
|
else
|
if(!burst_act) next_state = SD_RD_W2;
|
if(!burst_act) next_state = SD_RD_W2;
|
end
|
end
|
|
|
SD_RD_W2: //32
|
SD_RD_W2:
|
begin
|
begin
|
if(wb_cycle & wb_write_go) next_state = IDLE;
|
if(wb_write_go | ack_cnt_is_0)
|
|
begin
|
|
if(!ap_en & !kro) next_state = BT_W;
|
else
|
else
|
if(!wb_cycle | ack_cnt_is_0) next_state = IDLE;
|
if(!wb_wait & !mem_ack_r) next_state = IDLE_T;
|
|
end
|
end
|
end
|
|
|
BT: // Burst Terminate C
|
BT:
|
begin
|
begin
|
cmd = `MC_CMD_BT;
|
cmd = `MC_CMD_BT;
|
tmr_ld_trp = 1'b1;
|
tmr_ld_trp = 1'b1;
|
if(cmd_asserted) next_state = BT_W;
|
if(cmd_asserted) next_state = BT_W;
|
end
|
end
|
|
|
BT_W: // D
|
BT_W:
|
begin
|
begin
|
if(kro) next_state = IDLE;
|
cmd_a10 = cmd_a10_r; // Hold Auto Precharge 'til cycle finishes
|
else
|
|
if(tmr_done & (!burst_fp | kro)) next_state = IDLE;
|
if(kro & tmr_done)
|
|
begin
|
|
if(kro & !wb_wait & (wb_read_go | wb_write_go) ) cs_le_d = 1'b1;
|
|
next_state = IDLE;
|
|
end
|
else
|
else
|
if(tmr_done & burst_fp & !kro) // Must PRECHARGE Full Page Bursts
|
if(!kro & tmr_done) // Must do a PRECHARGE after Burst Terminate
|
begin
|
begin
|
bank_clr = 1'b1;
|
bank_clr = 1'b1;
|
cmd = `MC_CMD_PC;
|
cmd = `MC_CMD_PC;
|
cmd_a10 = `MC_SINGLE_BANK;
|
cmd_a10 = `MC_SINGLE_BANK;
|
tmr_ld_trp = 1'b1;
|
tmr_ld_trp = 1'b1;
|
| Line 1419... |
Line 1486... |
end
|
end
|
end
|
end
|
|
|
REFR: // Refresh Cycle
|
REFR: // Refresh Cycle
|
begin
|
begin
|
cs_le = 1'b1;
|
cs_le_d = 1'b1;
|
cmd = `MC_CMD_ARFR;
|
cmd = `MC_CMD_ARFR;
|
tmr_ld_trfc = 1'b1;
|
tmr_ld_trfc = 1'b1;
|
rfr_ack = 1'b1;
|
rfr_ack = 1'b1;
|
if(cmd_asserted)
|
if(cmd_asserted)
|
begin
|
begin
|
| Line 1457... |
Line 1524... |
if(cmd_asserted) next_state = IDLE_T;
|
if(cmd_asserted) next_state = IDLE_T;
|
end
|
end
|
|
|
INIT0:
|
INIT0:
|
begin
|
begin
|
cs_le = 1'b1;
|
cs_le_d = 1'b1;
|
next_state = INIT;
|
next_state = INIT;
|
end
|
end
|
|
|
INIT: // Initialize SDRAMS
|
INIT: // Initialize SDRAMS
|
begin // PRECHARGE
|
begin // PRECHARGE
|
| Line 1490... |
Line 1557... |
ir_cnt_dec = 1'b1;
|
ir_cnt_dec = 1'b1;
|
next_state = INIT_REFR1_W;
|
next_state = INIT_REFR1_W;
|
end
|
end
|
end
|
end
|
|
|
INIT_REFR1_W: // 21
|
INIT_REFR1_W:
|
begin
|
begin
|
init_ack = 1'b1;
|
init_ack = 1'b1;
|
if(tmr_done)
|
if(tmr_done)
|
begin
|
begin
|
if(ir_cnt_done) next_state = INIT_LMR;
|
if(ir_cnt_done) next_state = INIT_LMR;
|
| Line 1521... |
Line 1588... |
next_state = BG1;
|
next_state = BG1;
|
end
|
end
|
BG1:
|
BG1:
|
begin // Bus Grant
|
begin // Bus Grant
|
mc_bg = 1'b1;
|
mc_bg = 1'b1;
|
cs_le = 1'b1;
|
cs_le_d = 1'b1;
|
mc_c_oe_d = 1'b0;
|
mc_c_oe_d = 1'b0;
|
next_state = BG2;
|
next_state = BG2;
|
end
|
end
|
BG2:
|
BG2:
|
begin // Bus Grant
|
begin // Bus Grant
|
|
cs_le_d = 1'b1;
|
mc_bg = !wb_read_go & !wb_write_go &
|
mc_bg = !wb_read_go & !wb_write_go &
|
!rfr_req & !init_req & !lmr_req &
|
!rfr_req & !init_req & !lmr_req &
|
!susp_req_r;
|
!susp_req_r;
|
tmr_ld_tcl = 1'b1;
|
tmr_ld_tavav = 1'b1;
|
|
mc_c_oe_d = mc_br;
|
if(!mc_br) next_state = IDLE_T;
|
if(!mc_br) next_state = IDLE_T;
|
else mc_c_oe_d = 1'b0;
|
|
end
|
end
|
|
|
/////////////////////////////////////////
|
/////////////////////////////////////////
|
// SUSPEND/RESUME STATES ....
|
// SUSPEND/RESUME STATES ....
|
/////////////////////////////////////////
|
/////////////////////////////////////////
|
