| Line 9... |
Line 9... |
//// ////
|
//// ////
|
//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
|
//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
|
//// ////
|
//// ////
|
/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Rudolf Usselmann ////
|
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
|
|
//// www.asics.ws ////
|
//// rudi@asics.ws ////
|
//// rudi@asics.ws ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
| Line 35... |
Line 36... |
//// ////
|
//// ////
|
/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
|
|
// CVS Log
|
// CVS Log
|
//
|
//
|
// $Id: mc_timing.v,v 1.7 2001-12-21 05:09:30 rudi Exp $
|
// $Id: mc_timing.v,v 1.8 2002-01-21 13:08:52 rudi Exp $
|
//
|
//
|
// $Date: 2001-12-21 05:09:30 $
|
// $Date: 2002-01-21 13:08:52 $
|
// $Revision: 1.7 $
|
// $Revision: 1.8 $
|
// $Author: rudi $
|
// $Author: rudi $
|
// $Locker: $
|
// $Locker: $
|
// $State: Exp $
|
// $State: Exp $
|
//
|
//
|
// Change History:
|
// Change History:
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.7 2001/12/21 05:09:30 rudi
|
|
//
|
|
// - Fixed combinatorial loops in synthesis
|
|
// - Fixed byte select bug
|
|
//
|
// Revision 1.6 2001/12/11 02:47:19 rudi
|
// Revision 1.6 2001/12/11 02:47:19 rudi
|
//
|
//
|
// - Made some changes not to expect clock during reset ...
|
// - Made some changes not to expect clock during reset ...
|
//
|
//
|
// Revision 1.5 2001/11/29 02:16:28 rudi
|
// Revision 1.5 2001/11/29 02:16:28 rudi
|
| Line 128... |
Line 134... |
// Memory Interface
|
// Memory Interface
|
mc_clk, data_oe, oe_, we_, cas_, ras_, cke_,
|
mc_clk, data_oe, oe_, we_, cas_, ras_, cke_,
|
cs_en, wb_cycle, wr_cycle,
|
cs_en, wb_cycle, wr_cycle,
|
mc_br, mc_bg, mc_adsc, mc_adv,
|
mc_br, mc_bg, mc_adsc, mc_adv,
|
mc_c_oe, mc_ack,
|
mc_c_oe, mc_ack,
|
|
not_mem_cyc,
|
|
|
// Register File Interface
|
// Register File Interface
|
csc, tms, cs, lmr_req, lmr_ack, cs_le_d, cs_le,
|
csc, tms, cs, lmr_req, lmr_ack, cs_le_d, cs_le,
|
|
|
// Address Select Signals
|
// Address Select Signals
|
| Line 183... |
Line 190... |
output mc_bg;
|
output mc_bg;
|
output mc_adsc;
|
output mc_adsc;
|
output mc_adv;
|
output mc_adv;
|
output mc_c_oe;
|
output mc_c_oe;
|
input mc_ack;
|
input mc_ack;
|
|
input not_mem_cyc;
|
|
|
// Register File Interface
|
// Register File Interface
|
input [31:0] csc;
|
input [31:0] csc;
|
input [31:0] tms;
|
input [31:0] tms;
|
input [7:0] cs;
|
input [7:0] cs;
|
| Line 575... |
Line 583... |
// Indicates when the row_same and bank_open lookups are done
|
// Indicates when the row_same and bank_open lookups are done
|
reg lookup_ready1a;
|
reg lookup_ready1a;
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if(rst) lookup_ready1 <= #1 1'b0;
|
if(rst) lookup_ready1 <= #1 1'b0;
|
else lookup_ready1 <= #1 cs_le & wb_stb_i;
|
else lookup_ready1 <= #1 cs_le & wb_cyc_i & wb_stb_i;
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if(rst) lookup_ready2 <= #1 1'b0;
|
if(rst) lookup_ready2 <= #1 1'b0;
|
else lookup_ready2 <= #1 lookup_ready1 & wb_stb_i;
|
else lookup_ready2 <= #1 lookup_ready1 & wb_cyc_i & wb_stb_i;
|
|
|
// Keep Track if it is a SDRAM write cycle
|
// Keep Track if it is a SDRAM write cycle
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if(rst) wr_cycle <= #1 1'b0;
|
if(rst) wr_cycle <= #1 1'b0;
|
else
|
else
|
| Line 595... |
Line 603... |
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if(rst) wb_cycle <= #1 1'b0;
|
if(rst) wb_cycle <= #1 1'b0;
|
else
|
else
|
if(wb_cycle_set) wb_cycle <= #1 1'b1;
|
if(wb_cycle_set) wb_cycle <= #1 1'b1;
|
else
|
else
|
if(!wb_cyc_i) wb_cycle <= #1 1'b0;
|
if(!wb_cyc_i | not_mem_cyc) wb_cycle <= #1 1'b0;
|
|
|
// Thses two signals are used to signal that no wishbone cycle is in
|
// Thses two signals are used to signal that no wishbone cycle is in
|
// progress. Need to register them to avoid a very long combinatorial
|
// progress. Need to register them to avoid a very long combinatorial
|
// path ....
|
// path ....
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
| Line 640... |
Line 648... |
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if(rst) rfr_ack_r <= #1 1'b0;
|
if(rst) rfr_ack_r <= #1 1'b0;
|
else rfr_ack_r <= #1 rfr_ack_d;
|
else rfr_ack_r <= #1 rfr_ack_d;
|
|
|
// Suspend Select Logic
|
// Suspend Select Logic
|
//assign susp_sel = susp_sel_r | susp_sel_set;
|
|
assign susp_sel = susp_sel_r;
|
assign susp_sel = susp_sel_r;
|
|
|
always @(posedge clk or posedge rst)
|
always @(posedge clk or posedge rst)
|
if(rst) susp_sel_r <= #1 1'b0;
|
if(rst) susp_sel_r <= #1 1'b0;
|
else
|
else
|
| Line 886... |
Line 893... |
if(tmr_done) next_state = IDLE;
|
if(tmr_done) next_state = IDLE;
|
end
|
end
|
`endif
|
`endif
|
IDLE:
|
IDLE:
|
begin
|
begin
|
cs_le_d = wb_stb_first | lmr_req;
|
//cs_le_d = wb_stb_first | lmr_req;
|
|
cs_le_d = wb_stb_first;
|
|
|
burst_cnt_ld = 1'b1;
|
burst_cnt_ld = 1'b1;
|
wr_clr = 1'b1;
|
wr_clr = 1'b1;
|
|
|
if(mem_type == `MC_MEM_TYPE_SCS) tmr2_ld_tscsto = 1'b1;
|
if(mem_type == `MC_MEM_TYPE_SCS) tmr2_ld_tscsto = 1'b1;
|
if(mem_type == `MC_MEM_TYPE_SRAM) tmr2_ld_tsrdv = 1'b1;
|
if(mem_type == `MC_MEM_TYPE_SRAM) tmr2_ld_tsrdv = 1'b1;
|
|
|
|
|
if(rfr_req)
|
if(rfr_req)
|
begin
|
begin
|
rfr_ack_d = 1'b1;
|
rfr_ack_d = 1'b1;
|
next_state = PRECHARGE;
|
next_state = PRECHARGE;
|
end
|
end
|
| Line 1011... |
Line 1019... |
|
|
IDLE_T2:
|
IDLE_T2:
|
begin
|
begin
|
if(tmr2_done & (!wb_wait | !wb_cycle) )
|
if(tmr2_done & (!wb_wait | !wb_cycle) )
|
begin
|
begin
|
//cs_le_d = 1'b1;
|
cs_le_d = wb_cycle;
|
//if(cs_le_r) next_state = IDLE;
|
if(cs_le_r | !wb_cycle) next_state = IDLE;
|
cs_le_d = wb_stb_i;
|
|
if(cs_le_r | !wb_stb_i) next_state = IDLE;
|
|
end
|
end
|
end
|
end
|
|
|
/////////////////////////////////////////
|
/////////////////////////////////////////
|
// SCS STATES ....
|
// SCS STATES ....
|
| Line 1138... |
Line 1144... |
end
|
end
|
end
|
end
|
|
|
SRAM_RD4: // DESELECT
|
SRAM_RD4: // DESELECT
|
begin
|
begin
|
|
if(wb_cycle) cs_le_d = 1'b1; // For RMW
|
mc_adsc = 1'b1;
|
mc_adsc = 1'b1;
|
next_state = IDLE;
|
next_state = IDLE;
|
end
|
end
|
|
|
SRAM_WR:
|
SRAM_WR:
|
