OpenCores

Rev 4	Rev 8
Line 35...	Line 35...
`//// ////`	`//// ////`
`/////////////////////////////////////////////////////////////////////`	`/////////////////////////////////////////////////////////////////////`

`// CVS Log`	`// CVS Log`
`//`	`//`
`// $Id: mc_timing.v,v 1.1 2001-07-29 07:34:41 rudi Exp $`	`// $Id: mc_timing.v,v 1.2 2001-08-10 08:16:21 rudi Exp $`
`//`	`//`
`// $Date: 2001-07-29 07:34:41 $`	`// $Date: 2001-08-10 08:16:21 $`
`// $Revision: 1.1 $`	`// $Revision: 1.2 $`
`// $Author: rudi $`	`// $Author: rudi $`
`// $Locker: $`	`// $Locker: $`
`// $State: Exp $`	`// $State: Exp $`
`//`	`//`
`// Change History:`	`// Change History:`
`// $Log: not supported by cvs2svn $`	`// $Log: not supported by cvs2svn $`
	`// Revision 1.1 2001/07/29 07:34:41 rudi`
	`//`
	`//`
	`// 1) Changed Directory Structure`
	`// 2) Fixed several minor bugs`
	`//`
`// Revision 1.4 2001/06/14 01:57:37 rudi`	`// Revision 1.4 2001/06/14 01:57:37 rudi`
`//`	`//`
`//`	`//`
`// Fixed a potential bug in a corner case situation where the TMS register`	`// Fixed a potential bug in a corner case situation where the TMS register`
`// does not propegate properly during initialisation.`	`// does not propegate properly during initialisation.`
Line 91...	Line 97...

`// Suspend/Resume Interface`	`// Suspend/Resume Interface`
`susp_req, resume_req, suspended, susp_sel,`	`susp_req, resume_req, suspended, susp_sel,`

`// Memory Interface`	`// Memory Interface`
`mc_clk, data_oe, oe_, we_, cas_, ras_, cke_,`	`data_oe, oe_, we_, cas_, ras_, cke_,`
`cs_en, wb_cycle, wr_cycle,`	`cs_en, wb_cycle, wr_cycle,`
`mc_br, mc_bg, mc_adsc, mc_adv,`	`mc_br, mc_bg, mc_adsc, mc_adv,`
`mc_c_oe, mc_ack,`	`mc_c_oe, mc_ack,`

`// Register File Interface`	`// Register File Interface`
Line 134...	Line 140...
`input resume_req;`	`input resume_req;`
`output suspended;`	`output suspended;`
`output susp_sel;`	`output susp_sel;`

`// Memory Interface`	`// Memory Interface`
`input mc_clk;`
`output data_oe;`	`output data_oe;`
`output oe_;`	`output oe_;`
`output we_;`	`output we_;`
`output cas_;`	`output cas_;`
`output ras_;`	`output ras_;`
Line 191...	Line 196...
`////////////////////////////////////////////////////////////////////`	`////////////////////////////////////////////////////////////////////`
`//`	`//`
`// Defines & Parameters`	`// Defines & Parameters`
`//`	`//`

`// Command Valid, Ras_, Cas_, We_`
`define CMD_NOP 4'b0111
`define CMD_PC 4'b1010
`define CMD_ACT 4'b1011
`define CMD_WR 4'b1100
`define CMD_RD 4'b1101
`define CMD_BT 4'b1110
`define CMD_ARFR 4'b1001
`define CMD_LMR 4'b1000
`define CMD_XRD 4'b1111
`define CMD_XWR 4'b1110

`define SINGLE_BANK 1'b0
`define ALL_BANKS 1'b1

`// Number of states: 66`	`// Number of states: 66`
`parameter [65:0] // synopsys enum state`	`parameter [65:0] // synopsys enum state`
`POR = 66'b000000000000000000000000000000000000000000000000000000000000000001,`	`POR = 66'b000000000000000000000000000000000000000000000000000000000000000001,`
`IDLE = 66'b000000000000000000000000000000000000000000000000000000000000000010,`	`IDLE = 66'b000000000000000000000000000000000000000000000000000000000000000010,`
`IDLE_T = 66'b000000000000000000000000000000000000000000000000000000000000000100,`	`IDLE_T = 66'b000000000000000000000000000000000000000000000000000000000000000100,`
Line 385...	Line 375...
`wire bw8, bw16;`	`wire bw8, bw16;`

`reg mc_c_oe_d;`	`reg mc_c_oe_d;`
`reg mc_c_oe;`	`reg mc_c_oe;`

	`reg mc_le;`

`////////////////////////////////////////////////////////////////////`	`////////////////////////////////////////////////////////////////////`
`//`	`//`
`// Aliases`	`// Aliases`
`//`	`//`
`assign mem_type = csc[3:1];`	`assign mem_type = csc[3:1];`
Line 404...	Line 396...
`// Control Signals Output Enable`	`// Control Signals Output Enable`
`always @(posedge clk or negedge rst)`	`always @(posedge clk or negedge rst)`
`if(!rst) mc_c_oe <= #1 1'b0;`	`if(!rst) mc_c_oe <= #1 1'b0;`
`else mc_c_oe <= mc_c_oe_d;`	`else mc_c_oe <= mc_c_oe_d;`

	`always @(posedge clk or negedge rst)`
	`if(!rst) mc_le <= #1 1'b0;`
	`else mc_le <= #1 ~mc_le;`

`always @(posedge clk)`	`always @(posedge clk)`
`pack_le0 <= #1 pack_le0_d;`	`pack_le0 <= #1 pack_le0_d;`

`always @(posedge clk)`	`always @(posedge clk)`
`pack_le1 <= #1 pack_le1_d;`	`pack_le1 <= #1 pack_le1_d;`

`always @(posedge clk)`	`always @(posedge clk)`
`pack_le2 <= #1 pack_le2_d;`	`pack_le2 <= #1 pack_le2_d;`

`always @(posedge mc_clk)`	`always @(posedge clk)`
`mc_adv_r1 <= #1 mc_adv;`	`if(!mc_le) mc_adv_r1 <= #1 mc_adv;`

`always @(posedge mc_clk)`	`always @(posedge clk)`
`mc_adv_r <= #1 mc_adv_r1;`	`if(!mc_le) mc_adv_r <= #1 mc_adv_r1;`

`// Bus Width decoder`	`// Bus Width decoder`
assign bw8 = (bus_width == `BW_8);	assign bw8 = (bus_width == `MC_BW_8);
assign bw16 = (bus_width == `BW_16);	assign bw16 = (bus_width == `MC_BW_16);

`assign cs_a = \|cs; // Any Chip Select`	`assign cs_a = \|cs; // Any Chip Select`

`// Memory to Wishbone Ack`	`// Memory to Wishbone Ack`
`always @(posedge clk)`	`always @(posedge clk)`
Line 442...	Line 438...
`cmd_del <= #1 cmd_r;`	`cmd_del <= #1 cmd_r;`

`assign {cs_en, ras_, cas_, we_} = wr_cycle ? cmd_del : cmd;`	`assign {cs_en, ras_, cas_, we_} = wr_cycle ? cmd_del : cmd;`

`// Track Timing of Asserting a command`	`// Track Timing of Asserting a command`
`always @(posedge mc_clk)`	`always @(posedge clk)`
`cmd_asserted <= #1 cmd[3];`	`if(!mc_le) cmd_asserted <= #1 cmd[3];`

`always @(posedge mc_clk)`	`always @(posedge clk)`
`cmd_asserted2 <= #1 cmd_asserted;`	`if(mc_le) cmd_asserted2 <= #1 cmd_asserted;`

`// Output Enable`	`// Output Enable`
`always @(posedge clk)`	`always @(posedge clk)`
`oe_ <= #1 ~oe_d;`	`oe_ <= #1 ~oe_d;`

Line 563...	Line 559...
`if(tmr2_ld_trdv) timer2 <= #1 { tms[7:0], 1'b1};`	`if(tmr2_ld_trdv) timer2 <= #1 { tms[7:0], 1'b1};`
`else`	`else`
`if(!timer2_is_zero) timer2 <= #1 timer2 - 9'b1;`	`if(!timer2_is_zero) timer2 <= #1 timer2 - 9'b1;`

`wire twd_is_zero;`	`wire twd_is_zero;`
`assign twd_is_zero = tms[19:16] == 0;`	`assign twd_is_zero = (tms[19:16] == 4'h0);`

`assign timer2_is_zero = (timer2 == 9'h0);`	`assign timer2_is_zero = (timer2 == 9'h0);`

`always @(posedge clk)`	`always @(posedge clk)`
`tmr2_done <= #1 timer2_is_zero & !tmr2_ld_trdv & !tmr2_ld_trdz &`	`tmr2_done <= #1 timer2_is_zero & !tmr2_ld_trdv & !tmr2_ld_trdz &`
`!tmr2_ld_twpw & !tmr2_ld_twd & !tmr2_ld_twwd & !tmr2_ld_tscsto;`	`!tmr2_ld_twpw & !tmr2_ld_twd & !tmr2_ld_twwd & !tmr2_ld_tscsto;`

`// SDRAM Memories timing tracker`	`// SDRAM Memories timing tracker`
`always @(posedge mc_clk or negedge rst)`	`always @(posedge clk or negedge rst)`
`ifdef POR_DELAY	`ifdef MC_POR_DELAY
if(!rst) timer <= #1 `POR_DELAY_VAL ;	if(!rst) timer <= #1 `MC_POR_DELAY_VAL ;
`else`	`else`
`endif	`endif
`if(tmr_ld_twr2) timer <= #1 { 4'h0, tms[15:12] };`	`if(tmr_ld_twr2) timer <= #1 { 4'h0, tms[15:12] };`
`else`	`else`
`if(tmr_ld_trdz) timer <= #1 { 4'h0, tms[11:8] };`	`if(tmr_ld_trdz) timer <= #1 { 4'h0, tms[11:8] };`
Line 595...	Line 591...
`else`	`else`
`if(tmr_ld_trfc) timer <= #1 { 4'h0, tms[27:24]};`	`if(tmr_ld_trfc) timer <= #1 { 4'h0, tms[27:24]};`
`else`	`else`
`if(tmr_ld_txsr) timer <= #1 8'd7;`	`if(tmr_ld_txsr) timer <= #1 8'd7;`
`else`	`else`
`if(!timer_is_zero) timer <= #1 timer - 8'b1;`	`if(!timer_is_zero & !mc_le) timer <= #1 timer - 8'b1;`

`assign timer_is_zero = (timer == 8'h0);`	`assign timer_is_zero = (timer == 8'h0);`

`always @(posedge clk)`	`always @(posedge clk)`
`tmr_done <= #1 timer_is_zero;`	`tmr_done <= #1 timer_is_zero;`

`// Init Refresh Cycles Counter`	`// Init Refresh Cycles Counter`
`always @(posedge clk)`	`always @(posedge clk)`
if(ir_cnt_ld) ir_cnt <= #1 `INIT_RFRC_CNT;	if(ir_cnt_ld) ir_cnt <= #1 `MC_INIT_RFRC_CNT;
`else`	`else`
`if(ir_cnt_dec) ir_cnt <= #1 ir_cnt - 4'b1;`	`if(ir_cnt_dec) ir_cnt <= #1 ir_cnt - 4'b1;`

`always @(posedge clk)`	`always @(posedge clk)`
`ir_cnt_done <= #1 (ir_cnt == 4'h0);`	`ir_cnt_done <= #1 (ir_cnt == 4'h0);`
Line 645...	Line 641...
`//`	`//`
`// Main State Machine`	`// Main State Machine`
`//`	`//`

`always @(posedge clk or negedge rst)`	`always @(posedge clk or negedge rst)`
`ifdef POR_DELAY	`ifdef MC_POR_DELAY
`if(!rst) state <= #1 POR;`	`if(!rst) state <= #1 POR;`
`else	`else
`if(!rst) state <= #1 IDLE;`	`if(!rst) state <= #1 IDLE;`
`endif	`endif
`else state <= #1 next_state;`	`else state <= #1 next_state;`
Line 667...	Line 663...
`)`	`)`
`begin`	`begin`
`next_state = state; // Default keep current state`	`next_state = state; // Default keep current state`
`cnt_next = 1'b0;`	`cnt_next = 1'b0;`

cmd = `CMD_NOP;	cmd = `MC_CMD_NOP;
`cmd_a10 = ~kro;`	`cmd_a10 = ~kro;`
`oe_d = 1'b0;`	`oe_d = 1'b0;`
`data_oe_d = 1'b0;`	`data_oe_d = 1'b0;`
`cke_d = 1'b1;`	`cke_d = 1'b1;`
`cke_rd = 1'b1;`	`cke_rd = 1'b1;`
Line 729...	Line 725...
`pack_le2_d = 1'b0;`	`pack_le2_d = 1'b0;`

`mc_c_oe_d = 1'b1;`	`mc_c_oe_d = 1'b1;`

`case(state) // synopsys full_case parallel_case`	`case(state) // synopsys full_case parallel_case`
`ifdef POR_DELAY	`ifdef MC_POR_DELAY
`POR:`	`POR:`
`begin`	`begin`
`if(tmr_done) next_state = IDLE;`	`if(tmr_done) next_state = IDLE;`
`end`	`end`
`endif	`endif
Line 771...	Line 767...
`else`	`else`
`if(cs_a & (wb_read_go \| wb_write_go) & (lookup_ready1 \| wb_cycle) )`	`if(cs_a & (wb_read_go \| wb_write_go) & (lookup_ready1 \| wb_cycle) )`
`begin`	`begin`
`wb_cycle_set = 1'b1;`	`wb_cycle_set = 1'b1;`
`case(mem_type) // synopsys full_case parallel_case`	`case(mem_type) // synopsys full_case parallel_case`
`MEM_TYPE_SDRAM: // SDRAM	`MC_MEM_TYPE_SDRAM: // SDRAM
`if((lookup_ready2 \| wb_cycle) & !wb_wait)`	`if((lookup_ready2 \| wb_cycle) & !wb_wait)`
`begin`	`begin`
`if(wb_write_go \| wb_we_i) wr_set = 1'b1;`	`if(wb_write_go \| wb_we_i) wr_set = 1'b1;`
`if(kro & bank_open & row_same) next_state = SD_RD_WR;`	`if(kro & bank_open & row_same) next_state = SD_RD_WR;`
`else`	`else`
`if(kro & bank_open) next_state = PRECHARGE;`	`if(kro & bank_open) next_state = PRECHARGE;`
`else next_state = ACTIVATE;`	`else next_state = ACTIVATE;`
`end`	`end`
`MEM_TYPE_ACS:	`MC_MEM_TYPE_ACS:
`begin // Async Chip Select`	`begin // Async Chip Select`
`if(!wb_wait)`	`if(!wb_wait)`
`begin`	`begin`
`cs_le = 1'b1;`	`cs_le = 1'b1;`
`if(wb_write_go)`	`if(wb_write_go)`
Line 793...	Line 789...
`next_state = ACS_WR;`	`next_state = ACS_WR;`
`end`	`end`
`else next_state = ACS_RD;`	`else next_state = ACS_RD;`
`end`	`end`
`end`	`end`
`MEM_TYPE_SCS:	`MC_MEM_TYPE_SCS:
`begin // Sync Chip Select`	`begin // Sync Chip Select`
`if(!wb_wait)`	`if(!wb_wait)`
`begin`	`begin`
`tmr2_ld_tscsto = 1'b1;`	`tmr2_ld_tscsto = 1'b1;`
`cs_le = 1'b1;`	`cs_le = 1'b1;`
`if(wb_write_go)`	`if(wb_write_go)`
`begin`	`begin`
cmd = `CMD_XWR;	cmd = `MC_CMD_XWR;
`data_oe_d = 1'b1;`	`data_oe_d = 1'b1;`
`tmr_ld_twr2 = 1'b1;`	`tmr_ld_twr2 = 1'b1;`
`next_state = SCS_WR;`	`next_state = SCS_WR;`
`end`	`end`
`else`	`else`
`begin`	`begin`
cmd = `CMD_XRD;	cmd = `MC_CMD_XRD;
`oe_d = 1'b1;`	`oe_d = 1'b1;`
`tmr_ld_trdv = 1'b1;`	`tmr_ld_trdv = 1'b1;`
`next_state = SCS_RD;`	`next_state = SCS_RD;`
`end`	`end`
`end`	`end`
`end`	`end`
`MEM_TYPE_SRAM:	`MC_MEM_TYPE_SRAM:
`begin // SRAM`	`begin // SRAM`
`if(!wb_wait)`	`if(!wb_wait)`
`begin`	`begin`
`cs_le = 1'b1;`	`cs_le = 1'b1;`
`if(wb_write_go)`	`if(wb_write_go)`
Line 828...	Line 824...
`mem_ack_d = 1'b1;`	`mem_ack_d = 1'b1;`
`next_state = SRAM_WR;`	`next_state = SRAM_WR;`
`end`	`end`
`else`	`else`
`begin`	`begin`
cmd = `CMD_XRD;	cmd = `MC_CMD_XRD;
`oe_d = 1'b1;`	`oe_d = 1'b1;`
`mc_adsc = 1'b1;`	`mc_adsc = 1'b1;`
`tmr2_ld_tsrdv = 1'b1;`	`tmr2_ld_tsrdv = 1'b1;`
`next_state = SRAM_RD;`	`next_state = SRAM_RD;`
`end`	`end`
Line 860...	Line 856...
`/////////////////////////////////////////`	`/////////////////////////////////////////`
`// SCS STATES ....`	`// SCS STATES ....`
`/////////////////////////////////////////`	`/////////////////////////////////////////`
`SCS_RD:`	`SCS_RD:`
`begin`	`begin`
cmd = `CMD_XRD;	cmd = `MC_CMD_XRD;
`oe_d = 1'b1;`	`oe_d = 1'b1;`
`tmr_ld_trdv = 1'b1;`	`tmr_ld_trdv = 1'b1;`
`if(mc_ack) next_state = SCS_RD1;`	`if(mc_ack) next_state = SCS_RD1;`
`else`	`else`
`if(tmr2_done) next_state = SCS_ERR;`	`if(tmr2_done) next_state = SCS_ERR;`
`end`	`end`

`SCS_RD1:`	`SCS_RD1:`
`begin`	`begin`
cmd = `CMD_XRD;	cmd = `MC_CMD_XRD;
`oe_d = 1'b1;`	`oe_d = 1'b1;`
`if(tmr_done)`	`if(tmr_done)`
`begin`	`begin`
`mem_ack_d = 1'b1;`	`mem_ack_d = 1'b1;`
`tmr_ld_trdz = 1'b1;`	`tmr_ld_trdz = 1'b1;`
Line 889...	Line 885...
`end`	`end`

`SCS_WR:`	`SCS_WR:`
`begin`	`begin`
`tmr_ld_twr2 = 1'b1;`	`tmr_ld_twr2 = 1'b1;`
cmd = `CMD_XWR;	cmd = `MC_CMD_XWR;
`data_oe_d = 1'b1;`	`data_oe_d = 1'b1;`
`if(mc_ack) next_state = SCS_WR1;`	`if(mc_ack) next_state = SCS_WR1;`
`else`	`else`
`if(tmr2_done) next_state = SCS_ERR;`	`if(tmr2_done) next_state = SCS_ERR;`
`end`	`end`
Line 904...	Line 900...
`if(tmr_done)`	`if(tmr_done)`
`begin`	`begin`
`mem_ack_d = 1'b1;`	`mem_ack_d = 1'b1;`
`next_state = IDLE_T;`	`next_state = IDLE_T;`
`end`	`end`
else cmd = `CMD_XWR;	else cmd = `MC_CMD_XWR;
`end`	`end`

`SCS_ERR:`	`SCS_ERR:`
`begin`	`begin`
`mem_ack_d = 1'b1;`	`mem_ack_d = 1'b1;`
Line 920...	Line 916...
`// SSRAM STATES ....`	`// SSRAM STATES ....`
`/////////////////////////////////////////`	`/////////////////////////////////////////`

`SRAM_RD:`	`SRAM_RD:`
`begin`	`begin`
cmd = `CMD_XRD;	cmd = `MC_CMD_XRD;
`oe_d = 1'b1;`	`oe_d = 1'b1;`
`mc_adsc = 1'b1;`	`mc_adsc = 1'b1;`
`tmr2_ld_tsrdv = 1'b1;`	`tmr2_ld_tsrdv = 1'b1;`
`burst_cnt_ld_4 = 1'b1;`	`burst_cnt_ld_4 = 1'b1;`
`if(cmd_asserted) next_state = SRAM_RD0;`	`if(cmd_asserted) next_state = SRAM_RD0;`
Line 982...	Line 978...
`next_state = IDLE;`	`next_state = IDLE;`
`end`	`end`

`SRAM_WR: // 80`	`SRAM_WR: // 80`
`begin`	`begin`
cmd = `CMD_XWR;	cmd = `MC_CMD_XWR;
`mc_adsc = 1'b1;`	`mc_adsc = 1'b1;`
`data_oe_d = 1'b1;`	`data_oe_d = 1'b1;`
`if(cmd_asserted)`	`if(cmd_asserted)`
`begin`	`begin`
`if(wb_wait) next_state = SRAM_WR0;`	`if(wb_wait) next_state = SRAM_WR0;`
Line 1027...	Line 1023...
`/////////////////////////////////////////`	`/////////////////////////////////////////`
`// Async Devices STATES ....`	`// Async Devices STATES ....`
`/////////////////////////////////////////`	`/////////////////////////////////////////`
`ACS_RD:`	`ACS_RD:`
`begin`	`begin`
cmd = `CMD_XRD;	cmd = `MC_CMD_XRD;
`oe_d = 1'b1;`	`oe_d = 1'b1;`
`tmr2_ld_trdv = 1'b1;`	`tmr2_ld_trdv = 1'b1;`
`next_state = ACS_RD1;`	`next_state = ACS_RD1;`
`end`	`end`

`ACS_RD1:`	`ACS_RD1:`
`begin // 32 bit, 8 bit - first; 16 bit - first`	`begin // 32 bit, 8 bit - first; 16 bit - first`
cmd = `CMD_XRD;	cmd = `MC_CMD_XRD;
`oe_d = 1'b1;`	`oe_d = 1'b1;`
`if(tmr2_done)`	`if(tmr2_done)`
`begin`	`begin`
`if(bw8 \| bw16) next_adr = 1'b1;`	`if(bw8 \| bw16) next_adr = 1'b1;`
`if(bw8) next_state = ACS_RD_8_1;`	`if(bw8) next_state = ACS_RD_8_1;`
Line 1051...	Line 1047...
`end`	`end`

`ACS_RD_8_1:`	`ACS_RD_8_1:`
`begin // 8 bit 2nd byte`	`begin // 8 bit 2nd byte`
`pack_le0_d = 1'b1;`	`pack_le0_d = 1'b1;`
cmd = `CMD_XRD;	cmd = `MC_CMD_XRD;
`oe_d = 1'b1;`	`oe_d = 1'b1;`
`tmr2_ld_trdv = 1'b1;`	`tmr2_ld_trdv = 1'b1;`
`next_state = ACS_RD_8_2;`	`next_state = ACS_RD_8_2;`
`end`	`end`

`ACS_RD_8_2:`	`ACS_RD_8_2:`
`begin`	`begin`
cmd = `CMD_XRD;	cmd = `MC_CMD_XRD;
`oe_d = 1'b1;`	`oe_d = 1'b1;`
`if(tmr2_done)`	`if(tmr2_done)`
`begin`	`begin`
`next_adr = 1'b1;`	`next_adr = 1'b1;`
`next_state = ACS_RD_8_3;`	`next_state = ACS_RD_8_3;`
Line 1071...	Line 1067...
`end`	`end`

`ACS_RD_8_3:`	`ACS_RD_8_3:`
`begin // 8 bit 3rd byte`	`begin // 8 bit 3rd byte`
`pack_le1_d = 1'b1;`	`pack_le1_d = 1'b1;`
cmd = `CMD_XRD;	cmd = `MC_CMD_XRD;
`oe_d = 1'b1;`	`oe_d = 1'b1;`
`tmr2_ld_trdv = 1'b1;`	`tmr2_ld_trdv = 1'b1;`
`next_state = ACS_RD_8_4;`	`next_state = ACS_RD_8_4;`
`end`	`end`

`ACS_RD_8_4:`	`ACS_RD_8_4:`
`begin`	`begin`
cmd = `CMD_XRD;	cmd = `MC_CMD_XRD;
`oe_d = 1'b1;`	`oe_d = 1'b1;`
`if(tmr2_done)`	`if(tmr2_done)`
`begin`	`begin`
`next_adr = 1'b1;`	`next_adr = 1'b1;`
`next_state = ACS_RD_8_5;`	`next_state = ACS_RD_8_5;`
Line 1092...	Line 1088...

`ACS_RD_8_5:`	`ACS_RD_8_5:`
`begin // 8 bit 4th byte; 16 bit 2nd word`	`begin // 8 bit 4th byte; 16 bit 2nd word`
`if(bw8) pack_le2_d = 1'b1;`	`if(bw8) pack_le2_d = 1'b1;`
`if(bw16) pack_le0_d = 1'b1;`	`if(bw16) pack_le0_d = 1'b1;`
cmd = `CMD_XRD;	cmd = `MC_CMD_XRD;
`oe_d = 1'b1;`	`oe_d = 1'b1;`
`tmr2_ld_trdv = 1'b1;`	`tmr2_ld_trdv = 1'b1;`
`next_state = ACS_RD_8_6;`	`next_state = ACS_RD_8_6;`
`end`	`end`

`ACS_RD_8_6:`	`ACS_RD_8_6:`
`begin`	`begin`
cmd = `CMD_XRD;	cmd = `MC_CMD_XRD;
`oe_d = 1'b1;`	`oe_d = 1'b1;`
`if(tmr2_done)`	`if(tmr2_done)`
`begin`	`begin`
`next_state = ACS_RD2;`	`next_state = ACS_RD2;`
`end`	`end`
`end`	`end`

`ACS_RD2A:`	`ACS_RD2A:`
`begin`	`begin`
`oe_d = 1'b1;`	`oe_d = 1'b1;`
cmd = `CMD_XRD;	cmd = `MC_CMD_XRD;
`next_state = ACS_RD2;`	`next_state = ACS_RD2;`
`end`	`end`

`ACS_RD2:`	`ACS_RD2:`
`begin`	`begin`
cmd = `CMD_XRD;	cmd = `MC_CMD_XRD;
`next_state = ACS_RD3;`	`next_state = ACS_RD3;`
`end`	`end`

`ACS_RD3:`	`ACS_RD3:`
`begin`	`begin`
Line 1131...	Line 1127...
`end`	`end`

`ACS_WR:`	`ACS_WR:`
`begin`	`begin`
`tmr2_ld_twpw = 1'b1;`	`tmr2_ld_twpw = 1'b1;`
cmd = `CMD_XWR;	cmd = `MC_CMD_XWR;
`data_oe_d = 1'b1;`	`data_oe_d = 1'b1;`
`next_state = ACS_WR1;`	`next_state = ACS_WR1;`
`end`	`end`

`ACS_WR1:`	`ACS_WR1:`
`begin`	`begin`
`if(!cmd_asserted) tmr2_ld_twpw = 1'b1;`	`if(!cmd_asserted) tmr2_ld_twpw = 1'b1;`
cmd = `CMD_XWR;	cmd = `MC_CMD_XWR;
`data_oe_d = 1'b1;`	`data_oe_d = 1'b1;`
`if(tmr2_done)`	`if(tmr2_done)`
`begin`	`begin`
`tmr2_ld_twd = 1'b1;`	`tmr2_ld_twd = 1'b1;`
`next_state = ACS_WR2;`	`next_state = ACS_WR2;`
Line 1153...	Line 1149...
`ACS_WR2:`	`ACS_WR2:`
`begin`	`begin`
`if(twd_is_zero) next_state = ACS_WR3;`	`if(twd_is_zero) next_state = ACS_WR3;`
`else`	`else`
`begin`	`begin`
cmd = `CMD_XRD;	cmd = `MC_CMD_XRD;
`data_oe_d = 1'b1;`	`data_oe_d = 1'b1;`
`next_state = ACS_WR3;`	`next_state = ACS_WR3;`
`end`	`end`
`end`	`end`

`ACS_WR3:`	`ACS_WR3:`
`begin`	`begin`
`if(tmr2_done) next_state = ACS_WR4;`	`if(tmr2_done) next_state = ACS_WR4;`
else cmd = `CMD_XRD;	else cmd = `MC_CMD_XRD;
`end`	`end`

`ACS_WR4:`	`ACS_WR4:`
`begin`	`begin`
`tmr2_ld_twwd = 1'b1;`	`tmr2_ld_twwd = 1'b1;`
Line 1178...	Line 1174...
`// SDRAM STATES ....`	`// SDRAM STATES ....`
`/////////////////////////////////////////`	`/////////////////////////////////////////`

`PRECHARGE:`	`PRECHARGE:`
`begin`	`begin`

Line 35...

////                                                             ////

////                                                             ////

/////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////

//  CVS Log

//  CVS Log

//

//

//  $Id: mc_timing.v,v 1.1 2001-07-29 07:34:41 rudi Exp $

//  $Id: mc_timing.v,v 1.2 2001-08-10 08:16:21 rudi Exp $

//

//

//  $Date: 2001-07-29 07:34:41 $

//  $Date: 2001-08-10 08:16:21 $

//  $Revision: 1.1 $

//  $Revision: 1.2 $

//  $Author: rudi $

//  $Author: rudi $

//  $Locker:  $

//  $Locker:  $

//  $State: Exp $

//  $State: Exp $

//

//

// Change History:

// Change History:

//               $Log: not supported by cvs2svn $

//               $Log: not supported by cvs2svn $

//               Revision 1.1  2001/07/29 07:34:41  rudi

//

//

//               1) Changed Directory Structure

//               2) Fixed several minor bugs

//

//               Revision 1.4  2001/06/14 01:57:37  rudi

//               Revision 1.4  2001/06/14 01:57:37  rudi

//

//

//

//

//               Fixed a potential bug in a corner case situation where the TMS register

//               Fixed a potential bug in a corner case situation where the TMS register

//               does not propegate properly during initialisation.

//               does not propegate properly during initialisation.

Line 91...

Line 97...

                // Suspend/Resume Interface

                // Suspend/Resume Interface

                susp_req, resume_req, suspended, susp_sel,

                susp_req, resume_req, suspended, susp_sel,

                // Memory Interface

                // Memory Interface

                mc_clk, data_oe, oe_, we_, cas_, ras_, cke_,

                data_oe, oe_, we_, cas_, ras_, cke_,

                cs_en, wb_cycle, wr_cycle,

                cs_en, wb_cycle, wr_cycle,

                mc_br, mc_bg, mc_adsc, mc_adv,

                mc_br, mc_bg, mc_adsc, mc_adv,

                mc_c_oe, mc_ack,

                mc_c_oe, mc_ack,

                // Register File Interface

                // Register File Interface

Line 134...

Line 140...

input           resume_req;

input           resume_req;

output          suspended;

output          suspended;

output          susp_sel;

output          susp_sel;

// Memory Interface

// Memory Interface

input           mc_clk;

output          data_oe;

output          data_oe;

output          oe_;

output          oe_;

output          we_;

output          we_;

output          cas_;

output          cas_;

output          ras_;

output          ras_;

Line 191...

Line 196...

////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////

//

//

// Defines & Parameters

// Defines & Parameters

//

//

// Command Valid, Ras_, Cas_, We_

`define CMD_NOP         4'b0111

`define CMD_PC          4'b1010

`define CMD_ACT         4'b1011

`define CMD_WR          4'b1100

`define CMD_RD          4'b1101

`define CMD_BT          4'b1110

`define CMD_ARFR        4'b1001

`define CMD_LMR         4'b1000

`define CMD_XRD         4'b1111

`define CMD_XWR         4'b1110

`define SINGLE_BANK     1'b0

`define ALL_BANKS       1'b1

// Number of states: 66

// Number of states: 66

parameter       [65:0]   // synopsys enum state

parameter       [65:0]   // synopsys enum state

POR             = 66'b000000000000000000000000000000000000000000000000000000000000000001,

POR             = 66'b000000000000000000000000000000000000000000000000000000000000000001,

IDLE            = 66'b000000000000000000000000000000000000000000000000000000000000000010,

IDLE            = 66'b000000000000000000000000000000000000000000000000000000000000000010,

IDLE_T          = 66'b000000000000000000000000000000000000000000000000000000000000000100,

IDLE_T          = 66'b000000000000000000000000000000000000000000000000000000000000000100,

Line 385...

Line 375...

wire            bw8, bw16;

wire            bw8, bw16;

reg             mc_c_oe_d;

reg             mc_c_oe_d;

reg             mc_c_oe;

reg             mc_c_oe;

reg             mc_le;

////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////

//

//

// Aliases

// Aliases

//

//

assign mem_type  = csc[3:1];

assign mem_type  = csc[3:1];

Line 404...

Line 396...

// Control Signals Output Enable

// Control Signals Output Enable

always @(posedge clk or negedge rst)

always @(posedge clk or negedge rst)

        if(!rst)        mc_c_oe <= #1 1'b0;

        if(!rst)        mc_c_oe <= #1 1'b0;

        else            mc_c_oe <= mc_c_oe_d;

        else            mc_c_oe <= mc_c_oe_d;

always @(posedge clk or negedge rst)

        if(!rst)        mc_le <= #1 1'b0;

        else            mc_le <= #1 ~mc_le;

always @(posedge clk)

always @(posedge clk)

        pack_le0 <= #1 pack_le0_d;

        pack_le0 <= #1 pack_le0_d;

always @(posedge clk)

always @(posedge clk)

        pack_le1 <= #1 pack_le1_d;

        pack_le1 <= #1 pack_le1_d;

always @(posedge clk)

always @(posedge clk)

        pack_le2 <= #1 pack_le2_d;

        pack_le2 <= #1 pack_le2_d;

always @(posedge mc_clk)

always @(posedge clk)

        mc_adv_r1 <= #1 mc_adv;

        if(!mc_le)      mc_adv_r1 <= #1 mc_adv;

always @(posedge mc_clk)

always @(posedge clk)

        mc_adv_r <= #1 mc_adv_r1;

        if(!mc_le)      mc_adv_r <= #1 mc_adv_r1;

// Bus Width decoder

// Bus Width decoder

assign bw8  = (bus_width == `BW_8);

assign bw8  = (bus_width == `MC_BW_8);

assign bw16 = (bus_width == `BW_16);

assign bw16 = (bus_width == `MC_BW_16);

assign  cs_a = |cs;     // Any Chip Select

assign  cs_a = |cs;     // Any Chip Select

// Memory to Wishbone Ack

// Memory to Wishbone Ack

always @(posedge clk)

always @(posedge clk)

Line 442...

Line 438...

        cmd_del <= #1 cmd_r;

        cmd_del <= #1 cmd_r;

assign {cs_en, ras_, cas_, we_} = wr_cycle ? cmd_del : cmd;

assign {cs_en, ras_, cas_, we_} = wr_cycle ? cmd_del : cmd;

// Track Timing of Asserting a command

// Track Timing of Asserting a command

always @(posedge mc_clk)

always @(posedge clk)

        cmd_asserted <= #1 cmd[3];

        if(!mc_le)      cmd_asserted <= #1 cmd[3];

always @(posedge mc_clk)

always @(posedge clk)

        cmd_asserted2 <= #1 cmd_asserted;

        if(mc_le)       cmd_asserted2 <= #1 cmd_asserted;

// Output Enable

// Output Enable

always @(posedge clk)

always @(posedge clk)

        oe_ <= #1 ~oe_d;

        oe_ <= #1 ~oe_d;

Line 563...

Line 559...

        if(tmr2_ld_trdv)        timer2 <= #1 { tms[7:0], 1'b1};

        if(tmr2_ld_trdv)        timer2 <= #1 { tms[7:0], 1'b1};

        else

        else

        if(!timer2_is_zero)     timer2 <= #1 timer2 - 9'b1;

        if(!timer2_is_zero)     timer2 <= #1 timer2 - 9'b1;

wire    twd_is_zero;

wire    twd_is_zero;

assign twd_is_zero =  tms[19:16] == 0;

assign twd_is_zero =  (tms[19:16] == 4'h0);

assign timer2_is_zero = (timer2 == 9'h0);

assign timer2_is_zero = (timer2 == 9'h0);

always @(posedge clk)

always @(posedge clk)

        tmr2_done <= #1 timer2_is_zero & !tmr2_ld_trdv & !tmr2_ld_trdz &

        tmr2_done <= #1 timer2_is_zero & !tmr2_ld_trdv & !tmr2_ld_trdz &

                        !tmr2_ld_twpw & !tmr2_ld_twd & !tmr2_ld_twwd & !tmr2_ld_tscsto;

                        !tmr2_ld_twpw & !tmr2_ld_twd & !tmr2_ld_twwd & !tmr2_ld_tscsto;

// SDRAM Memories timing tracker

// SDRAM Memories timing tracker

always @(posedge mc_clk or negedge rst)

always @(posedge clk or negedge rst)

`ifdef POR_DELAY

`ifdef MC_POR_DELAY

        if(!rst)                timer <= #1 `POR_DELAY_VAL ;

        if(!rst)                timer <= #1 `MC_POR_DELAY_VAL ;

        else

        else

`endif

`endif

        if(tmr_ld_twr2)         timer <= #1 { 4'h0, tms[15:12] };

        if(tmr_ld_twr2)         timer <= #1 { 4'h0, tms[15:12] };

        else

        else

        if(tmr_ld_trdz)         timer <= #1 { 4'h0, tms[11:8] };

        if(tmr_ld_trdz)         timer <= #1 { 4'h0, tms[11:8] };

Line 595...

Line 591...

        else

        else

        if(tmr_ld_trfc)         timer <= #1 { 4'h0, tms[27:24]};

        if(tmr_ld_trfc)         timer <= #1 { 4'h0, tms[27:24]};

        else

        else

        if(tmr_ld_txsr)         timer <= #1 8'd7;

        if(tmr_ld_txsr)         timer <= #1 8'd7;

        else

        else

        if(!timer_is_zero)      timer <= #1 timer - 8'b1;

        if(!timer_is_zero & !mc_le)     timer <= #1 timer - 8'b1;

assign timer_is_zero = (timer == 8'h0);

assign timer_is_zero = (timer == 8'h0);

always @(posedge clk)

always @(posedge clk)

        tmr_done <= #1 timer_is_zero;

        tmr_done <= #1 timer_is_zero;

// Init Refresh Cycles Counter

// Init Refresh Cycles Counter

always @(posedge clk)

always @(posedge clk)

        if(ir_cnt_ld)   ir_cnt <= #1 `INIT_RFRC_CNT;

        if(ir_cnt_ld)   ir_cnt <= #1 `MC_INIT_RFRC_CNT;

        else

        else

        if(ir_cnt_dec)  ir_cnt <= #1 ir_cnt - 4'b1;

        if(ir_cnt_dec)  ir_cnt <= #1 ir_cnt - 4'b1;

always @(posedge clk)

always @(posedge clk)

        ir_cnt_done <= #1 (ir_cnt == 4'h0);

        ir_cnt_done <= #1 (ir_cnt == 4'h0);

Line 645...

Line 641...

//

//

// Main State Machine

// Main State Machine

//

//

always @(posedge clk or negedge rst)

always @(posedge clk or negedge rst)

`ifdef POR_DELAY

`ifdef MC_POR_DELAY

        if(!rst)        state <= #1 POR;

        if(!rst)        state <= #1 POR;

`else

`else

        if(!rst)        state <= #1 IDLE;

        if(!rst)        state <= #1 IDLE;

`endif

`endif

        else            state <= #1 next_state;

        else            state <= #1 next_state;

Line 667...

Line 663...

   begin

   begin

        next_state = state;     // Default keep current state

        next_state = state;     // Default keep current state

        cnt_next = 1'b0;

        cnt_next = 1'b0;

        cmd = `CMD_NOP;

        cmd = `MC_CMD_NOP;

        cmd_a10 = ~kro;

        cmd_a10 = ~kro;

        oe_d = 1'b0;

        oe_d = 1'b0;

        data_oe_d = 1'b0;

        data_oe_d = 1'b0;

        cke_d = 1'b1;

        cke_d = 1'b1;

        cke_rd = 1'b1;

        cke_rd = 1'b1;

Line 729...

Line 725...

        pack_le2_d = 1'b0;

        pack_le2_d = 1'b0;

        mc_c_oe_d = 1'b1;

        mc_c_oe_d = 1'b1;

        case(state)             // synopsys full_case parallel_case

        case(state)             // synopsys full_case parallel_case

`ifdef POR_DELAY

`ifdef MC_POR_DELAY

           POR:

           POR:

              begin

              begin

                if(tmr_done)    next_state = IDLE;

                if(tmr_done)    next_state = IDLE;

end

end

`endif

`endif

Line 771...

Line 767...

                else

                else

                if(cs_a & (wb_read_go | wb_write_go) & (lookup_ready1 | wb_cycle) )

                if(cs_a & (wb_read_go | wb_write_go) & (lookup_ready1 | wb_cycle) )

                  begin

                  begin

                   wb_cycle_set = 1'b1;

                   wb_cycle_set = 1'b1;

                   case(mem_type)               // synopsys full_case parallel_case

                   case(mem_type)               // synopsys full_case parallel_case

                     `MEM_TYPE_SDRAM:                   // SDRAM

                     `MC_MEM_TYPE_SDRAM:                // SDRAM

                        if((lookup_ready2 | wb_cycle) & !wb_wait)

                        if((lookup_ready2 | wb_cycle) & !wb_wait)

                           begin

                           begin

                                if(wb_write_go  | wb_we_i)      wr_set = 1'b1;

                                if(wb_write_go  | wb_we_i)      wr_set = 1'b1;

                                if(kro & bank_open & row_same)  next_state = SD_RD_WR;

                                if(kro & bank_open & row_same)  next_state = SD_RD_WR;

                                else

                                else

                                if(kro & bank_open)             next_state = PRECHARGE;

                                if(kro & bank_open)             next_state = PRECHARGE;

                                else                            next_state = ACTIVATE;

                                else                            next_state = ACTIVATE;

end

end

                     `MEM_TYPE_ACS:

                     `MC_MEM_TYPE_ACS:

                        begin                           // Async Chip Select

                        begin                           // Async Chip Select

                                if(!wb_wait)

                                if(!wb_wait)

                                   begin

                                   begin

                                        cs_le = 1'b1;

                                        cs_le = 1'b1;

                                        if(wb_write_go)

                                        if(wb_write_go)

Line 793...

Line 789...

                                                                next_state = ACS_WR;

                                                                next_state = ACS_WR;

end

end

                                        else                    next_state = ACS_RD;

                                        else                    next_state = ACS_RD;

end

end

end

end

                     `MEM_TYPE_SCS:

                     `MC_MEM_TYPE_SCS:

                        begin                           // Sync Chip Select

                        begin                           // Sync Chip Select

                                if(!wb_wait)

                                if(!wb_wait)

                                   begin

                                   begin

                                        tmr2_ld_tscsto = 1'b1;

                                        tmr2_ld_tscsto = 1'b1;

                                        cs_le = 1'b1;

                                        cs_le = 1'b1;

                                        if(wb_write_go)

                                        if(wb_write_go)

                                           begin

                                           begin

                                                cmd = `CMD_XWR;

                                                cmd = `MC_CMD_XWR;

                                                data_oe_d = 1'b1;

                                                data_oe_d = 1'b1;

                                                tmr_ld_twr2 = 1'b1;

                                                tmr_ld_twr2 = 1'b1;

                                                next_state = SCS_WR;

                                                next_state = SCS_WR;

end

end

                                        else

                                        else

                                           begin

                                           begin

                                                cmd = `CMD_XRD;

                                                cmd = `MC_CMD_XRD;

                                                oe_d = 1'b1;

                                                oe_d = 1'b1;

                                                tmr_ld_trdv = 1'b1;

                                                tmr_ld_trdv = 1'b1;

                                                next_state = SCS_RD;

                                                next_state = SCS_RD;

end

end

end

end

end

end

                     `MEM_TYPE_SRAM:

                     `MC_MEM_TYPE_SRAM:

                        begin           // SRAM

                        begin           // SRAM

                                if(!wb_wait)

                                if(!wb_wait)

                                   begin

                                   begin

                                        cs_le = 1'b1;

                                        cs_le = 1'b1;

                                        if(wb_write_go)

                                        if(wb_write_go)

Line 828...

Line 824...

                                                mem_ack_d = 1'b1;

                                                mem_ack_d = 1'b1;

                                                next_state = SRAM_WR;

                                                next_state = SRAM_WR;

end

end

                                        else

                                        else

                                           begin

                                           begin

                                                cmd = `CMD_XRD;

                                                cmd = `MC_CMD_XRD;

                                                oe_d = 1'b1;

                                                oe_d = 1'b1;

                                                mc_adsc = 1'b1;

                                                mc_adsc = 1'b1;

                                                tmr2_ld_tsrdv = 1'b1;

                                                tmr2_ld_tsrdv = 1'b1;

                                                next_state = SRAM_RD;

                                                next_state = SRAM_RD;

end

end

Line 860...

Line 856...

                /////////////////////////////////////////

                /////////////////////////////////////////

                // SCS STATES ....

                // SCS STATES ....

                /////////////////////////////////////////

                /////////////////////////////////////////

           SCS_RD:

           SCS_RD:

              begin

              begin

                cmd = `CMD_XRD;

                cmd = `MC_CMD_XRD;

                oe_d = 1'b1;

                oe_d = 1'b1;

                tmr_ld_trdv = 1'b1;

                tmr_ld_trdv = 1'b1;

                if(mc_ack)      next_state = SCS_RD1;

                if(mc_ack)      next_state = SCS_RD1;

                else

                else

                if(tmr2_done)   next_state = SCS_ERR;

                if(tmr2_done)   next_state = SCS_ERR;

end

end

           SCS_RD1:

           SCS_RD1:

              begin

              begin

                cmd = `CMD_XRD;

                cmd = `MC_CMD_XRD;

                oe_d = 1'b1;

                oe_d = 1'b1;

                if(tmr_done)

                if(tmr_done)

                   begin

                   begin

                        mem_ack_d = 1'b1;

                        mem_ack_d = 1'b1;

                        tmr_ld_trdz = 1'b1;

                        tmr_ld_trdz = 1'b1;

Line 889...

Line 885...

end

end

           SCS_WR:

           SCS_WR:

              begin

              begin

                tmr_ld_twr2 = 1'b1;

                tmr_ld_twr2 = 1'b1;

                cmd = `CMD_XWR;

                cmd = `MC_CMD_XWR;

                data_oe_d = 1'b1;

                data_oe_d = 1'b1;

                if(mc_ack)      next_state = SCS_WR1;

                if(mc_ack)      next_state = SCS_WR1;

                else

                else

                if(tmr2_done)   next_state = SCS_ERR;

                if(tmr2_done)   next_state = SCS_ERR;

end

end

Line 904...

Line 900...

                if(tmr_done)

                if(tmr_done)

                   begin

                   begin

                        mem_ack_d = 1'b1;

                        mem_ack_d = 1'b1;

                        next_state = IDLE_T;

                        next_state = IDLE_T;

end

end

                else    cmd = `CMD_XWR;

                else    cmd = `MC_CMD_XWR;

end

end

           SCS_ERR:

           SCS_ERR:

              begin

              begin

                mem_ack_d = 1'b1;

                mem_ack_d = 1'b1;

Line 920...

Line 916...

                // SSRAM STATES ....

                // SSRAM STATES ....

                /////////////////////////////////////////

                /////////////////////////////////////////

           SRAM_RD:

           SRAM_RD:

              begin

              begin

                cmd = `CMD_XRD;

                cmd = `MC_CMD_XRD;

                oe_d = 1'b1;

                oe_d = 1'b1;

                mc_adsc = 1'b1;

                mc_adsc = 1'b1;

                tmr2_ld_tsrdv = 1'b1;

                tmr2_ld_tsrdv = 1'b1;

                burst_cnt_ld_4 = 1'b1;

                burst_cnt_ld_4 = 1'b1;

                if(cmd_asserted)        next_state = SRAM_RD0;

                if(cmd_asserted)        next_state = SRAM_RD0;

Line 982...

Line 978...

                next_state = IDLE;

                next_state = IDLE;

end

end

           SRAM_WR: // 80

           SRAM_WR: // 80

              begin

              begin

                cmd = `CMD_XWR;

                cmd = `MC_CMD_XWR;

                mc_adsc = 1'b1;

                mc_adsc = 1'b1;

                data_oe_d = 1'b1;

                data_oe_d = 1'b1;

                if(cmd_asserted)

                if(cmd_asserted)

                   begin

                   begin

                        if(wb_wait)             next_state = SRAM_WR0;

                        if(wb_wait)             next_state = SRAM_WR0;

Line 1027...

Line 1023...

                /////////////////////////////////////////

                /////////////////////////////////////////

                // Async Devices STATES ....

                // Async Devices STATES ....

                /////////////////////////////////////////

                /////////////////////////////////////////

           ACS_RD:

           ACS_RD:

              begin

              begin

                cmd = `CMD_XRD;

                cmd = `MC_CMD_XRD;

                oe_d = 1'b1;

                oe_d = 1'b1;

                tmr2_ld_trdv = 1'b1;

                tmr2_ld_trdv = 1'b1;

                next_state = ACS_RD1;

                next_state = ACS_RD1;

end

end

           ACS_RD1:

           ACS_RD1:

              begin     // 32 bit, 8 bit - first; 16 bit - first

              begin     // 32 bit, 8 bit - first; 16 bit - first

                cmd = `CMD_XRD;

                cmd = `MC_CMD_XRD;

                oe_d = 1'b1;

                oe_d = 1'b1;

                if(tmr2_done)

                if(tmr2_done)

                   begin

                   begin

                        if(bw8 | bw16)          next_adr = 1'b1;

                        if(bw8 | bw16)          next_adr = 1'b1;

                        if(bw8)                 next_state = ACS_RD_8_1;

                        if(bw8)                 next_state = ACS_RD_8_1;

Line 1051...

Line 1047...

end

end

           ACS_RD_8_1:

           ACS_RD_8_1:

              begin     // 8 bit 2nd byte

              begin     // 8 bit 2nd byte

                pack_le0_d = 1'b1;

                pack_le0_d = 1'b1;

                cmd = `CMD_XRD;

                cmd = `MC_CMD_XRD;

                oe_d = 1'b1;

                oe_d = 1'b1;

                tmr2_ld_trdv = 1'b1;

                tmr2_ld_trdv = 1'b1;

                next_state = ACS_RD_8_2;

                next_state = ACS_RD_8_2;

end

end

           ACS_RD_8_2:

           ACS_RD_8_2:

              begin

              begin

                cmd = `CMD_XRD;

                cmd = `MC_CMD_XRD;

                oe_d = 1'b1;

                oe_d = 1'b1;

                if(tmr2_done)

                if(tmr2_done)

                   begin

                   begin

                        next_adr = 1'b1;

                        next_adr = 1'b1;

                        next_state = ACS_RD_8_3;

                        next_state = ACS_RD_8_3;

Line 1071...

Line 1067...

end

end

           ACS_RD_8_3:

           ACS_RD_8_3:

              begin     // 8 bit 3rd byte

              begin     // 8 bit 3rd byte

                pack_le1_d = 1'b1;

                pack_le1_d = 1'b1;

                cmd = `CMD_XRD;

                cmd = `MC_CMD_XRD;

                oe_d = 1'b1;

                oe_d = 1'b1;

                tmr2_ld_trdv = 1'b1;

                tmr2_ld_trdv = 1'b1;

                next_state = ACS_RD_8_4;

                next_state = ACS_RD_8_4;

end

end

           ACS_RD_8_4:

           ACS_RD_8_4:

              begin

              begin

                cmd = `CMD_XRD;

                cmd = `MC_CMD_XRD;

                oe_d = 1'b1;

                oe_d = 1'b1;

                if(tmr2_done)

                if(tmr2_done)

                   begin

                   begin

                        next_adr = 1'b1;

                        next_adr = 1'b1;

                        next_state = ACS_RD_8_5;

                        next_state = ACS_RD_8_5;

Line 1092...

Line 1088...

           ACS_RD_8_5:

           ACS_RD_8_5:

              begin     // 8 bit 4th byte; 16 bit 2nd word

              begin     // 8 bit 4th byte; 16 bit 2nd word

                if(bw8)                 pack_le2_d = 1'b1;

                if(bw8)                 pack_le2_d = 1'b1;

                if(bw16)                pack_le0_d = 1'b1;

                if(bw16)                pack_le0_d = 1'b1;

                cmd = `CMD_XRD;

                cmd = `MC_CMD_XRD;

                oe_d = 1'b1;

                oe_d = 1'b1;

                tmr2_ld_trdv = 1'b1;

                tmr2_ld_trdv = 1'b1;

                next_state = ACS_RD_8_6;

                next_state = ACS_RD_8_6;

end

end

           ACS_RD_8_6:

           ACS_RD_8_6:

              begin

              begin

                cmd = `CMD_XRD;

                cmd = `MC_CMD_XRD;

                oe_d = 1'b1;

                oe_d = 1'b1;

                if(tmr2_done)

                if(tmr2_done)

                   begin

                   begin

                        next_state = ACS_RD2;

                        next_state = ACS_RD2;

end

end

end

end

           ACS_RD2A:

           ACS_RD2A:

              begin

              begin

                oe_d = 1'b1;

                oe_d = 1'b1;

                cmd = `CMD_XRD;

                cmd = `MC_CMD_XRD;

                next_state = ACS_RD2;

                next_state = ACS_RD2;

end

end

           ACS_RD2:

           ACS_RD2:

              begin

              begin

                cmd = `CMD_XRD;

                cmd = `MC_CMD_XRD;

                next_state = ACS_RD3;

                next_state = ACS_RD3;

end

end

           ACS_RD3:

           ACS_RD3:

              begin

              begin

Line 1131...

Line 1127...

end

end

           ACS_WR:

           ACS_WR:

              begin

              begin

                tmr2_ld_twpw = 1'b1;

                tmr2_ld_twpw = 1'b1;

                cmd = `CMD_XWR;

                cmd = `MC_CMD_XWR;

                data_oe_d = 1'b1;

                data_oe_d = 1'b1;

                next_state = ACS_WR1;

                next_state = ACS_WR1;

end

end

           ACS_WR1:

           ACS_WR1:

              begin

              begin

                if(!cmd_asserted)       tmr2_ld_twpw = 1'b1;

                if(!cmd_asserted)       tmr2_ld_twpw = 1'b1;

                cmd = `CMD_XWR;

                cmd = `MC_CMD_XWR;

                data_oe_d = 1'b1;

                data_oe_d = 1'b1;

                if(tmr2_done)

                if(tmr2_done)

                   begin

                   begin

                        tmr2_ld_twd = 1'b1;

                        tmr2_ld_twd = 1'b1;

                        next_state = ACS_WR2;

                        next_state = ACS_WR2;

Line 1153...

Line 1149...

           ACS_WR2:

           ACS_WR2:

              begin

              begin

                if(twd_is_zero) next_state = ACS_WR3;

                if(twd_is_zero) next_state = ACS_WR3;

                else

                else

                   begin

                   begin

                        cmd = `CMD_XRD;

                        cmd = `MC_CMD_XRD;

                        data_oe_d = 1'b1;

                        data_oe_d = 1'b1;

                        next_state = ACS_WR3;

                        next_state = ACS_WR3;

end

end

end

end

           ACS_WR3:

           ACS_WR3:

              begin

              begin

                if(tmr2_done)   next_state = ACS_WR4;

                if(tmr2_done)   next_state = ACS_WR4;

                else            cmd = `CMD_XRD;

                else            cmd = `MC_CMD_XRD;

end

end

           ACS_WR4:

           ACS_WR4:

              begin

              begin

                tmr2_ld_twwd = 1'b1;

                tmr2_ld_twwd = 1'b1;

Line 1178...

Line 1174...

                // SDRAM STATES ....

                // SDRAM STATES ....

                /////////////////////////////////////////

                /////////////////////////////////////////

           PRECHARGE:

           PRECHARGE:

              begin

              begin

                cmd = `CMD_PC;

                cmd = `MC_CMD_PC;

                if(rfr_ack_r)

                if(rfr_ack_r)

                   begin

                   begin

                        rfr_ack = 1'b1;

                        rfr_ack = 1'b1;

                        cmd_a10 = `ALL_BANKS;

                        cmd_a10 = `MC_ALL_BANKS;

                        bank_clr_all = 1'b1;

                        bank_clr_all = 1'b1;

end

end

                else

                else

                   begin

                   begin

                        bank_clr = 1'b1;

                        bank_clr = 1'b1;

                        cmd_a10 = `SINGLE_BANK;

                        cmd_a10 = `MC_SINGLE_BANK;

end

end

                tmr_ld_trp = 1'b1;

                tmr_ld_trp = 1'b1;

                if(cmd_asserted)        next_state = PRECHARGE_W;

                if(cmd_asserted)        next_state = PRECHARGE_W;

end

end

Line 1210...

Line 1206...

              begin

              begin

                if(!wb_wait_r)

                if(!wb_wait_r)

                   begin

                   begin

                        row_sel = 1'b1;

                        row_sel = 1'b1;

                        tmr_ld_trcd = 1'b1;

                        tmr_ld_trcd = 1'b1;

                        cmd = `CMD_ACT;

                        cmd = `MC_CMD_ACT;

end

end

                if(cmd_asserted)        next_state = ACTIVATE_W;

                if(cmd_asserted)        next_state = ACTIVATE_W;

end

end

           ACTIVATE_W:

           ACTIVATE_W:

Line 1260...

Line 1256...

           SD_WR:       // Write Command A

           SD_WR:       // Write Command A

              begin     // Does the first single write

              begin     // Does the first single write

                data_oe_d = 1'b1;

                data_oe_d = 1'b1;

                tmr_ld_twr = 1'b1;

                tmr_ld_twr = 1'b1;

                cnt_next = ~cnt;

                cnt_next = ~cnt;

                cmd = `CMD_WR;

                cmd = `MC_CMD_WR;

                cmd_a10 = ~kro;

                cmd_a10 = ~kro;

                if(!cnt & wb_cycle & burst_act) cke_d = !wb_wait;

                if(!cnt & wb_cycle & burst_act) cke_d = !wb_wait;

                else                            cke_d = cke_r;

                else                            cke_d = cke_r;

Line 1287...

Line 1283...

                tmr_ld_twr = 1'b1;

                tmr_ld_twr = 1'b1;

                cnt_next = ~cnt;

                cnt_next = ~cnt;

                if(single_write & wb_cycle)

                if(single_write & wb_cycle)

                   begin

                   begin

                        cmd = `CMD_WR;

                        cmd = `MC_CMD_WR;

                        if(burst_act)   cmd_a10 = 1'b0;

                        if(burst_act)   cmd_a10 = 1'b0;

                        else            cmd_a10 = ~kro;

                        else            cmd_a10 = ~kro;

end

end

                data_oe_d = 1'b1;

                data_oe_d = 1'b1;

Line 1313...

Line 1309...

end

end

end

end

           SD_RD:       // Read Command 7

           SD_RD:       // Read Command 7

              begin

              begin

                cmd = `CMD_RD;

                cmd = `MC_CMD_RD;

                if(burst_fp)    cmd_a10 = 1'b0;

                if(burst_fp)    cmd_a10 = 1'b0;

                else            cmd_a10 = ~kro;

                else            cmd_a10 = ~kro;

                tmr_ld_tcl = 1'b1;

                tmr_ld_tcl = 1'b1;

                if(cmd_asserted)                        next_state = SD_RD_W;

                if(cmd_asserted)                        next_state = SD_RD_W;

end

end

Line 1351...

Line 1347...

                if(!wb_cycle | ack_cnt_is_0)            next_state = IDLE;

                if(!wb_cycle | ack_cnt_is_0)            next_state = IDLE;

end

end

           BT:          // Burst Terminate  C

           BT:          // Burst Terminate  C

              begin

              begin

                cmd = `CMD_BT;

                cmd = `MC_CMD_BT;

                tmr_ld_trp = 1'b1;

                tmr_ld_trp = 1'b1;

                if(cmd_asserted)                        next_state = BT_W;

                if(cmd_asserted)                        next_state = BT_W;

end

end

           BT_W:        // D

           BT_W:        // D

              begin

              begin

                if(kro)                                 next_state = IDLE;

                if(kro)                                 next_state = IDLE;

                else

                else

                if(tmr_done & (!burst_fp | kro))        next_state = IDLE;

                if(tmr_done & (!burst_fp | kro))        next_state = IDLE;

                else

                else

                if(tmr_done & burst_fp & ~kro)  // Must PRECHARGE Full Page Bursts

                if(tmr_done & burst_fp & !kro)  // Must PRECHARGE Full Page Bursts

                   begin

                   begin

                        bank_clr = 1'b1;

                        bank_clr = 1'b1;

                        cmd = `CMD_PC;

                        cmd = `MC_CMD_PC;

                        cmd_a10 = `SINGLE_BANK;

                        cmd_a10 = `MC_SINGLE_BANK;

                        tmr_ld_trp = 1'b1;

                        tmr_ld_trp = 1'b1;

                        if(cmd_asserted)                next_state = IDLE_T;

                        if(cmd_asserted)                next_state = IDLE_T;

end

end

end

end

           REFR:        // Refresh Cycle

           REFR:        // Refresh Cycle

              begin

              begin

                cmd = `CMD_ARFR;

                cmd = `MC_CMD_ARFR;

                tmr_ld_trfc = 1'b1;

                tmr_ld_trfc = 1'b1;

                rfr_ack = 1'b1;

                rfr_ack = 1'b1;

                if(cmd_asserted)                next_state = IDLE_T;

                if(cmd_asserted)                next_state = IDLE_T;

end

end

           LMR0:

           LMR0:

              begin

              begin

                lmr_ack = 1'b1;

                lmr_ack = 1'b1;

                cmd = `CMD_PC;

                cmd = `MC_CMD_PC;

                cmd_a10 = `ALL_BANKS;

                cmd_a10 = `MC_ALL_BANKS;

                bank_clr_all = 1'b1;

                bank_clr_all = 1'b1;

                tmr_ld_trp = 1'b1;

                tmr_ld_trp = 1'b1;

                if(cmd_asserted)                next_state = LMR1;

                if(cmd_asserted)                next_state = LMR1;

end

end

Line 1399...

Line 1395...

end

end

           LMR2:

           LMR2:

              begin

              begin

                bank_clr_all = 1'b1;

                bank_clr_all = 1'b1;

                cmd = `CMD_LMR;

                cmd = `MC_CMD_LMR;

                tmr_ld_trfc = 1'b1;

                tmr_ld_trfc = 1'b1;

                lmr_ack = 1'b1;

                lmr_ack = 1'b1;

                if(cmd_asserted)                next_state = IDLE_T;

                if(cmd_asserted)                next_state = IDLE_T;

end

end

Line 1414...

Line 1410...

end

end

           INIT:        // Initialize SDRAMS

           INIT:        // Initialize SDRAMS

              begin     // PRECHARGE

              begin     // PRECHARGE

                init_ack = 1'b1;

                init_ack = 1'b1;

                cmd = `CMD_PC;

                cmd = `MC_CMD_PC;

                cmd_a10 = `ALL_BANKS;

                cmd_a10 = `MC_ALL_BANKS;

                bank_clr_all = 1'b1;

                bank_clr_all = 1'b1;

                tmr_ld_trp = 1'b1;

                tmr_ld_trp = 1'b1;

                ir_cnt_ld = 1'b1;

                ir_cnt_ld = 1'b1;

                if(cmd_asserted)                next_state = INIT_W;

                if(cmd_asserted)                next_state = INIT_W;

end

end

Line 1431...

Line 1427...

end

end

           INIT_REFR1:  // Init Refresh Cycle 1

           INIT_REFR1:  // Init Refresh Cycle 1

              begin

              begin

                init_ack = 1'b1;

                init_ack = 1'b1;

                cmd = `CMD_ARFR;

                cmd = `MC_CMD_ARFR;

                tmr_ld_trfc = 1'b1;

                tmr_ld_trfc = 1'b1;

                if(cmd_asserted)

                if(cmd_asserted)

                   begin

                   begin

                        ir_cnt_dec = 1'b1;

                        ir_cnt_dec = 1'b1;

                        next_state = INIT_REFR1_W;

                        next_state = INIT_REFR1_W;

Line 1453...

Line 1449...

end

end

           INIT_LMR:

           INIT_LMR:

              begin

              begin

                init_ack = 1'b1;

                init_ack = 1'b1;

                cmd = `CMD_LMR;

                cmd = `MC_CMD_LMR;

                bank_clr_all = 1'b1;

                bank_clr_all = 1'b1;

                tmr_ld_trfc = 1'b1;

                tmr_ld_trfc = 1'b1;

                if(cmd_asserted)                next_state = IDLE_T;

                if(cmd_asserted)                next_state = IDLE_T;

end

end

Line 1490...

Line 1486...

                // SUSPEND/RESUME STATES ....

                // SUSPEND/RESUME STATES ....

                /////////////////////////////////////////

                /////////////////////////////////////////

           SUSP1:

           SUSP1:

              begin             // Precharge All

              begin             // Precharge All

                susp_sel = 1'b1;

                susp_sel = 1'b1;

                cmd = `CMD_PC;

                cmd = `MC_CMD_PC;

                cmd_a10 = `ALL_BANKS;

                cmd_a10 = `MC_ALL_BANKS;

                bank_clr_all = 1'b1;

                bank_clr_all = 1'b1;

                tmr_ld_trp = 1'b1;

                tmr_ld_trp = 1'b1;

                if(cmd_asserted)        next_state = SUSP2;

                if(cmd_asserted)        next_state = SUSP2;

end

end

Line 1507...

Line 1503...

           SUSP3:

           SUSP3:

              begin             // Enter Self refresh Mode

              begin             // Enter Self refresh Mode

                cke_d = 1'b0;

                cke_d = 1'b0;

                susp_sel = 1'b1;

                susp_sel = 1'b1;

                cmd = `CMD_ARFR;

                cmd = `MC_CMD_ARFR;

                rfr_ack = 1'b1;

                rfr_ack = 1'b1;

                if(cmd_asserted)

                if(cmd_asserted)

                   begin

                   begin

                        next_state = SUSP4;

                        next_state = SUSP4;

end

end

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[/] [mem_ctrl/] [trunk/] [rtl/] [verilog/] [mc_timing.v] - Diff between revs 4 and 8