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Line 9... |
//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
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//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Rudolf Usselmann ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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| Line 35... |
Line 36... |
//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: mc_top.v,v 1.6 2001-12-21 05:09:30 rudi Exp $
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// $Id: mc_top.v,v 1.7 2002-01-21 13:08:52 rudi Exp $
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//
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//
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// $Date: 2001-12-21 05:09:30 $
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// $Date: 2002-01-21 13:08:52 $
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// $Revision: 1.6 $
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// $Revision: 1.7 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.6 2001/12/21 05:09:30 rudi
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//
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// - Fixed combinatorial loops in synthesis
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// - Fixed byte select bug
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//
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// Revision 1.5 2001/11/29 02:16:28 rudi
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// Revision 1.5 2001/11/29 02:16:28 rudi
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//
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//
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//
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//
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// - More Synthesis cleanup, mostly for speed
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// - More Synthesis cleanup, mostly for speed
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// - Several bug fixes
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// - Several bug fixes
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| Line 267... |
Line 273... |
assign lmr_sel = lmr_ack | init_ack;
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assign lmr_sel = lmr_ack | init_ack;
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assign tms_s = lmr_sel ? sp_tms : tms;
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assign tms_s = lmr_sel ? sp_tms : tms;
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assign csc_s = lmr_sel ? sp_csc : csc;
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assign csc_s = lmr_sel ? sp_csc : csc;
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wire not_mem_cyc;
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assign not_mem_cyc = wb_cyc_i & wb_stb_i & !( `MC_MEM_SEL );
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reg mem_ack_r;
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always @(posedge clk_i)
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mem_ack_r <= #1 mem_ack;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Modules
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// Modules
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//
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//
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| Line 310... |
Line 326... |
mc_adr_sel u1(
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mc_adr_sel u1(
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.clk( clk_i ),
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.clk( clk_i ),
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.csc( csc_s ),
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.csc( csc_s ),
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.tms( tms_s ),
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.tms( tms_s ),
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.wb_stb_i( wb_stb_i ),
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.wb_stb_i( wb_stb_i ),
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.wb_ack_o( wb_ack_o ),
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//.wb_ack_o( wb_ack_o ),
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.wb_ack_o( mem_ack_r ),
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.wb_addr_i( wb_addr_i ),
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.wb_addr_i( wb_addr_i ),
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.wb_we_i( wb_we_i ),
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.wb_we_i( wb_we_i ),
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.wb_write_go( wb_write_go ),
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.wb_write_go( wb_write_go ),
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.wr_hold( wr_hold ),
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.wr_hold( wr_hold ),
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.cas_( cas_ ),
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.cas_( cas_ ),
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| Line 351... |
Line 368... |
.rst( rst_i ),
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.rst( rst_i ),
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.csc( csc ),
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.csc( csc ),
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.wb_cyc_i( wb_cyc_i ),
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.wb_cyc_i( wb_cyc_i ),
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.wb_stb_i( wb_stb_i ),
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.wb_stb_i( wb_stb_i ),
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.mem_ack( mem_ack ),
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.mem_ack( mem_ack ),
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.wb_ack_o( wb_ack_o ),
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//.wb_ack_o( wb_ack_o ),
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.wb_ack_o( mem_ack_r ),
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.wb_we_i( wb_we_i ),
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.wb_we_i( wb_we_i ),
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.wb_data_i( wb_data_i ),
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.wb_data_i( wb_data_i ),
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.wb_data_o( mem_dout ),
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.wb_data_o( mem_dout ),
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.wb_read_go( wb_read_go ),
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.wb_read_go( wb_read_go ),
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.mc_clk( mc_clk_i ),
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.mc_clk( mc_clk_i ),
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| Line 399... |
Line 417... |
.suspended( suspended_o ),
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.suspended( suspended_o ),
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.susp_sel( susp_sel ),
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.susp_sel( susp_sel ),
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.mc_br( mc_br_r ),
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.mc_br( mc_br_r ),
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.mc_bg( mc_bg_d ),
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.mc_bg( mc_bg_d ),
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.mc_ack( mc_ack_r ),
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.mc_ack( mc_ack_r ),
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.not_mem_cyc( not_mem_cyc ),
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.data_oe( data_oe ),
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.data_oe( data_oe ),
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.oe_( oe_ ),
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.oe_( oe_ ),
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.we_( we_ ),
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.we_( we_ ),
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.cas_( cas_ ),
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.cas_( cas_ ),
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.ras_( ras_ ),
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.ras_( ras_ ),
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