| Line 35... |
Line 35... |
//// ////
|
//// ////
|
/////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////
|
|
|
// CVS Log
|
// CVS Log
|
//
|
//
|
// $Id: mc_top.v,v 1.1 2001-07-29 07:34:41 rudi Exp $
|
// $Id: mc_top.v,v 1.2 2001-08-10 08:16:21 rudi Exp $
|
//
|
//
|
// $Date: 2001-07-29 07:34:41 $
|
// $Date: 2001-08-10 08:16:21 $
|
// $Revision: 1.1 $
|
// $Revision: 1.2 $
|
// $Author: rudi $
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// $Author: rudi $
|
// $Locker: $
|
// $Locker: $
|
// $State: Exp $
|
// $State: Exp $
|
//
|
//
|
// Change History:
|
// Change History:
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
|
// Revision 1.1 2001/07/29 07:34:41 rudi
|
|
//
|
|
//
|
|
// 1) Changed Directory Structure
|
|
// 2) Fixed several minor bugs
|
|
//
|
// Revision 1.3 2001/06/12 15:19:49 rudi
|
// Revision 1.3 2001/06/12 15:19:49 rudi
|
//
|
//
|
//
|
//
|
// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
|
// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
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//
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//
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| Line 74... |
Line 80... |
//
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//
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//
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//
|
|
|
`include "mc_defines.v"
|
`include "mc_defines.v"
|
|
|
module mc_top(clk, rst,
|
module mc_top(clk_i, rst_i,
|
|
|
wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
|
wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
|
wb_stb_i, wb_ack_o, wb_err_o,
|
wb_stb_i, wb_ack_o, wb_err_o,
|
|
|
susp_req, resume_req, suspended, poc,
|
susp_req_i, resume_req_i, suspended_o, poc_o,
|
|
|
mc_clk, mc_br, mc_bg, mc_ack,
|
mc_clk_i, mc_br_pad_i, mc_bg_pad_o, mc_ack_pad_i,
|
mc_addr, mc_data_i, mc_data_o, mc_dp_i, mc_dp_o, mc_data_oe,
|
mc_addr_pad_o, mc_data_pad_i, mc_data_pad_o, mc_dp_pad_i,
|
mc_dqm, mc_oe_, mc_we_, mc_cas_, mc_ras_, mc_cke_, mc_cs_, mc_sts,
|
mc_dp_pad_o, mc_doe_pad_doe_o, mc_dqm_pad_o, mc_oe_pad_o_,
|
mc_rp_, mc_vpen, mc_adsc_, mc_adv_, mc_zz, mc_c_oe
|
mc_we_pad_o_, mc_cas_pad_o_, mc_ras_pad_o_, mc_cke_pad_o_,
|
|
mc_cs_pad_o_, mc_sts_pad_i, mc_rp_pad_o_, mc_vpen_pad_o,
|
|
mc_adsc_pad_o_, mc_adv_pad_o_, mc_zz_pad_o, mc_coe_pad_coe_o
|
);
|
);
|
|
|
input clk, rst;
|
input clk_i, rst_i;
|
|
|
// --------------------------------------
|
// --------------------------------------
|
// WISHBONE SLAVE INTERFACE
|
// WISHBONE SLAVE INTERFACE
|
input [31:0] wb_data_i;
|
input [31:0] wb_data_i;
|
output [31:0] wb_data_o;
|
output [31:0] wb_data_o;
|
| Line 103... |
Line 111... |
output wb_ack_o;
|
output wb_ack_o;
|
output wb_err_o;
|
output wb_err_o;
|
|
|
// --------------------------------------
|
// --------------------------------------
|
// Suspend Resume Interface
|
// Suspend Resume Interface
|
input susp_req;
|
input susp_req_i;
|
input resume_req;
|
input resume_req_i;
|
output suspended;
|
output suspended_o;
|
|
|
// POC
|
// POC
|
output [31:0] poc;
|
output [31:0] poc_o;
|
|
|
// --------------------------------------
|
// --------------------------------------
|
// Memory Bus Signals
|
// Memory Bus Signals
|
input mc_clk;
|
input mc_clk_i;
|
input mc_br;
|
input mc_br_pad_i;
|
output mc_bg;
|
output mc_bg_pad_o;
|
input mc_ack;
|
input mc_ack_pad_i;
|
output [23:0] mc_addr;
|
output [23:0] mc_addr_pad_o;
|
input [31:0] mc_data_i;
|
input [31:0] mc_data_pad_i;
|
output [31:0] mc_data_o;
|
output [31:0] mc_data_pad_o;
|
input [3:0] mc_dp_i;
|
input [3:0] mc_dp_pad_i;
|
output [3:0] mc_dp_o;
|
output [3:0] mc_dp_pad_o;
|
output mc_data_oe;
|
output mc_doe_pad_doe_o;
|
output [3:0] mc_dqm;
|
output [3:0] mc_dqm_pad_o;
|
output mc_oe_;
|
output mc_oe_pad_o_;
|
output mc_we_;
|
output mc_we_pad_o_;
|
output mc_cas_;
|
output mc_cas_pad_o_;
|
output mc_ras_;
|
output mc_ras_pad_o_;
|
output mc_cke_;
|
output mc_cke_pad_o_;
|
output [7:0] mc_cs_;
|
output [7:0] mc_cs_pad_o_;
|
input mc_sts;
|
input mc_sts_pad_i;
|
output mc_rp_;
|
output mc_rp_pad_o_;
|
output mc_vpen;
|
output mc_vpen_pad_o;
|
output mc_adsc_;
|
output mc_adsc_pad_o_;
|
output mc_adv_;
|
output mc_adv_pad_o_;
|
output mc_zz;
|
output mc_zz_pad_o;
|
output mc_c_oe;
|
output mc_coe_pad_coe_o;
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Local Wires
|
// Local Wires
|
//
|
//
|
| Line 152... |
Line 160... |
wire mem_ack;
|
wire mem_ack;
|
wire mem_wb_ack_o, rf_wb_ack_o;
|
wire mem_wb_ack_o, rf_wb_ack_o;
|
|
|
// --------------------------------------
|
// --------------------------------------
|
// Suspend Resume Interface
|
// Suspend Resume Interface
|
wire susp_req;
|
//wire susp_req;
|
wire resume_req;
|
//wire resume_req;
|
wire susp_sel;
|
wire susp_sel;
|
|
reg mc_zz_pad_o;
|
|
|
// Register File Interconnects
|
// Register File Interconnects
|
wire [31:0] rf_dout;
|
wire [31:0] rf_dout;
|
wire [31:0] csc;
|
wire [31:0] csc;
|
wire [31:0] tms;
|
wire [31:0] tms;
|
| Line 233... |
Line 242... |
initial // FOR RICHARD TEST BENCH ONLY ... FIX_ME
|
initial // FOR RICHARD TEST BENCH ONLY ... FIX_ME
|
begin
|
begin
|
$shm_open("waves");
|
$shm_open("waves");
|
$shm_probe("AS",mc_top,"AS");
|
$shm_probe("AS",mc_top,"AS");
|
$display("INFO: Signal dump enabled ...\n\n");
|
$display("INFO: Signal dump enabled ...\n\n");
|
repeat(4000) @(posedge clk);
|
repeat(4000) @(posedge clk_i);
|
$finish;
|
$finish;
|
end
|
end
|
// synopsys translate_on
|
// synopsys translate_on
|
*/
|
*/
|
|
|
////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////
|
//
|
//
|
// Misc Logic
|
// Misc Logic
|
//
|
//
|
|
|
assign mc_rp_ = !suspended & !fs;
|
assign mc_rp_pad_o_ = !suspended_o & !fs;
|
assign mc_zz = suspended;
|
|
|
|
|
always @(posedge mc_clk_i)
|
|
mc_zz_pad_o <= #1 suspended_o;
|
|
|
assign wb_err_o = wb_cyc_i & wb_stb_i &
|
assign wb_err_o = wb_cyc_i & wb_stb_i &
|
(`MEM_SEL ? ((par_err & !wb_we_i) | err | wp_err) : rf_wb_err_o);
|
(`MC_MEM_SEL ? ((par_err & !wb_we_i) | err | wp_err) : rf_wb_err_o);
|
assign wb_data_o = `MEM_SEL ? mem_dout : rf_dout;
|
assign wb_data_o = `MC_MEM_SEL ? mem_dout : rf_dout;
|
assign wb_ack_o = `MEM_SEL ? mem_wb_ack_o : rf_wb_ack_o;
|
assign wb_ack_o = `MC_MEM_SEL ? mem_wb_ack_o : rf_wb_ack_o;
|
|
|
assign obct_cs = (rfr_ack | susp_sel) ? cs_need_rfr :
|
assign obct_cs = (rfr_ack | susp_sel) ? cs_need_rfr :
|
(lmr_ack | init_ack) ? spec_req_cs : cs;
|
(lmr_ack | init_ack) ? spec_req_cs : cs;
|
assign lmr_sel = lmr_ack | init_ack;
|
assign lmr_sel = lmr_ack | init_ack;
|
|
|
| Line 266... |
Line 276... |
//
|
//
|
// Modules
|
// Modules
|
//
|
//
|
|
|
mc_rf u0(
|
mc_rf u0(
|
.clk( clk ),
|
.clk( clk_i ),
|
.rst( rst ),
|
.rst( rst_i ),
|
.wb_data_i( wb_data_i ),
|
.wb_data_i( wb_data_i ),
|
.rf_dout( rf_dout ),
|
.rf_dout( rf_dout ),
|
.wb_addr_i( wb_addr_i ),
|
.wb_addr_i( wb_addr_i ),
|
.wb_we_i( wb_we_i ),
|
.wb_we_i( wb_we_i ),
|
.wb_cyc_i( wb_cyc_i ),
|
.wb_cyc_i( wb_cyc_i ),
|
| Line 279... |
Line 289... |
.wb_ack_o( rf_wb_ack_o ),
|
.wb_ack_o( rf_wb_ack_o ),
|
.wb_err_o( rf_wb_err_o ),
|
.wb_err_o( rf_wb_err_o ),
|
.wp_err( wp_err ),
|
.wp_err( wp_err ),
|
.csc( csc ),
|
.csc( csc ),
|
.tms( tms ),
|
.tms( tms ),
|
.poc( poc ),
|
.poc( poc_o ),
|
.sp_csc( sp_csc ),
|
.sp_csc( sp_csc ),
|
.sp_tms( sp_tms ),
|
.sp_tms( sp_tms ),
|
.cs( cs ),
|
.cs( cs ),
|
.mc_data_i( mc_data_i ),
|
.mc_data_i( mc_data_pad_i ),
|
.mc_sts( mc_sts ),
|
.mc_sts( mc_sts_pad_i ),
|
.mc_vpen( mc_vpen ),
|
.mc_vpen( mc_vpen_pad_o ),
|
.fs( fs ),
|
.fs( fs ),
|
.cs_le( cs_le ),
|
.cs_le( cs_le ),
|
.cs_need_rfr( cs_need_rfr ),
|
.cs_need_rfr( cs_need_rfr ),
|
.ref_int( ref_int ),
|
.ref_int( ref_int ),
|
.rfr_ps_val( rfr_ps_val ),
|
.rfr_ps_val( rfr_ps_val ),
|
| Line 299... |
Line 309... |
.lmr_req( lmr_req ),
|
.lmr_req( lmr_req ),
|
.lmr_ack( lmr_ack )
|
.lmr_ack( lmr_ack )
|
);
|
);
|
|
|
mc_adr_sel u1(
|
mc_adr_sel u1(
|
.clk( clk ),
|
.clk( clk_i ),
|
.csc( csc ),
|
.csc( csc_s ),
|
.tms( tms_s ),
|
.tms( tms_s ),
|
.wb_stb_i( wb_stb_i ),
|
.wb_stb_i( wb_stb_i ),
|
.wb_ack_o( mem_wb_ack_o ),
|
.wb_ack_o( mem_wb_ack_o ),
|
.wb_addr_i( wb_addr_i ),
|
.wb_addr_i( wb_addr_i ),
|
.wb_write_go( wb_write_go ),
|
.wb_write_go( wb_write_go ),
|
| Line 322... |
Line 332... |
.wr_cycle( wr_cycle ),
|
.wr_cycle( wr_cycle ),
|
.page_size( page_size )
|
.page_size( page_size )
|
);
|
);
|
|
|
mc_obct_top u2(
|
mc_obct_top u2(
|
.clk( clk ),
|
.clk( clk_i ),
|
.rst( rst ),
|
.rst( rst_i ),
|
.cs( obct_cs ),
|
.cs( obct_cs ),
|
.row_adr( row_adr ),
|
.row_adr( row_adr ),
|
.bank_adr( bank_adr ),
|
.bank_adr( bank_adr ),
|
.bank_set( bank_set ),
|
.bank_set( bank_set ),
|
.bank_clr( bank_clr ),
|
.bank_clr( bank_clr ),
|
| Line 337... |
Line 347... |
.row_same( row_same ),
|
.row_same( row_same ),
|
.rfr_ack( rfr_ack )
|
.rfr_ack( rfr_ack )
|
);
|
);
|
|
|
mc_dp u3(
|
mc_dp u3(
|
.clk( clk ),
|
.clk( clk_i ),
|
.rst( rst ),
|
.rst( rst_i ),
|
.csc( csc ),
|
.csc( csc ),
|
.wb_cyc_i( wb_cyc_i ),
|
.wb_cyc_i( wb_cyc_i ),
|
.mem_wb_ack_o( mem_wb_ack_o ),
|
.mem_wb_ack_o( mem_wb_ack_o ),
|
.wb_data_i( wb_data_i ),
|
.wb_data_i( wb_data_i ),
|
.wb_data_o( mem_dout ),
|
.wb_data_o( mem_dout ),
|
.wb_read_go( wb_read_go ),
|
.wb_read_go( wb_read_go ),
|
.mc_data_i( mc_data_i ),
|
.mc_data_i( mc_data_pad_i ),
|
.mc_dp_i( mc_dp_i ),
|
.mc_dp_i( mc_dp_pad_i ),
|
.mc_data_o( mc_data_od ),
|
.mc_data_o( mc_data_od ),
|
.mc_dp_o( mc_dp_od ),
|
.mc_dp_o( mc_dp_od ),
|
.dv( dv ),
|
.dv( dv ),
|
.pack_le0( pack_le0 ),
|
.pack_le0( pack_le0 ),
|
.pack_le1( pack_le1 ),
|
.pack_le1( pack_le1 ),
|
| Line 358... |
Line 368... |
.byte_en( wb_sel_i ),
|
.byte_en( wb_sel_i ),
|
.par_err( par_err )
|
.par_err( par_err )
|
);
|
);
|
|
|
mc_refresh u4(
|
mc_refresh u4(
|
.clk( clk ),
|
.clk( clk_i ),
|
.rst( rst ),
|
.rst( rst_i ),
|
.cs_need_rfr( cs_need_rfr ),
|
.cs_need_rfr( cs_need_rfr ),
|
.ref_int( ref_int ),
|
.ref_int( ref_int ),
|
.rfr_req( rfr_req ),
|
.rfr_req( rfr_req ),
|
.rfr_ack( rfr_ack ),
|
.rfr_ack( rfr_ack ),
|
.rfr_ps_val( rfr_ps_val )
|
.rfr_ps_val( rfr_ps_val )
|
);
|
);
|
|
|
mc_timing u5(
|
mc_timing u5(
|
.clk( clk ),
|
.clk( clk_i ),
|
.rst( rst ),
|
.rst( rst_i ),
|
.wb_cyc_i( wb_cyc_i ),
|
.wb_cyc_i( wb_cyc_i ),
|
.wb_we_i( wb_we_i ),
|
.wb_we_i( wb_we_i ),
|
.wb_read_go( wb_read_go ),
|
.wb_read_go( wb_read_go ),
|
.wb_write_go( wb_write_go ),
|
.wb_write_go( wb_write_go ),
|
.wb_first( wb_first ),
|
.wb_first( wb_first ),
|
.wb_wait( wb_wait ),
|
.wb_wait( wb_wait ),
|
.mem_ack( mem_ack ),
|
.mem_ack( mem_ack ),
|
.err( err ),
|
.err( err ),
|
.susp_req( susp_req ),
|
.susp_req( susp_req_i ),
|
.resume_req( resume_req ),
|
.resume_req( resume_req_i ),
|
.suspended( suspended ),
|
.suspended( suspended_o ),
|
.susp_sel( susp_sel ),
|
.susp_sel( susp_sel ),
|
.mc_clk( mc_clk ),
|
|
.mc_br( mc_br_r ),
|
.mc_br( mc_br_r ),
|
.mc_bg( mc_bg_d ),
|
.mc_bg( mc_bg_d ),
|
.mc_ack( mc_ack_r ),
|
.mc_ack( mc_ack_r ),
|
.data_oe( data_oe ),
|
.data_oe( data_oe ),
|
.oe_( oe_ ),
|
.oe_( oe_ ),
|
| Line 395... |
Line 404... |
.ras_( ras_ ),
|
.ras_( ras_ ),
|
.cke_( cke_ ),
|
.cke_( cke_ ),
|
.cs_en( cs_en ),
|
.cs_en( cs_en ),
|
.mc_adsc( mc_adsc_d ),
|
.mc_adsc( mc_adsc_d ),
|
.mc_adv( mc_adv_d ),
|
.mc_adv( mc_adv_d ),
|
.mc_c_oe( mc_c_oe ),
|
.mc_c_oe( mc_coe_pad_coe_o),
|
.wb_cycle( wb_cycle ),
|
.wb_cycle( wb_cycle ),
|
.wr_cycle( wr_cycle ),
|
.wr_cycle( wr_cycle ),
|
.csc( csc_s ),
|
.csc( csc_s ),
|
.tms( tms_s ),
|
.tms( tms_s ),
|
.cs( cs ),
|
.cs( cs ),
|
| Line 426... |
Line 435... |
.init_req( init_req ),
|
.init_req( init_req ),
|
.init_ack( init_ack )
|
.init_ack( init_ack )
|
);
|
);
|
|
|
mc_wb_if u6(
|
mc_wb_if u6(
|
.clk( clk ),
|
.clk( clk_i ),
|
.rst( rst ),
|
.rst( rst_i ),
|
.wb_addr_i( wb_addr_i ),
|
.wb_addr_i( wb_addr_i ),
|
.wb_cyc_i( wb_cyc_i ),
|
.wb_cyc_i( wb_cyc_i ),
|
.wb_stb_i( wb_stb_i ),
|
.wb_stb_i( wb_stb_i ),
|
.wb_we_i( wb_we_i ),
|
.wb_we_i( wb_we_i ),
|
.wb_ack_o( mem_wb_ack_o ),
|
.wb_ack_o( mem_wb_ack_o ),
|
| Line 443... |
Line 452... |
.mem_ack( mem_ack ),
|
.mem_ack( mem_ack ),
|
.wr_hold( wr_hold )
|
.wr_hold( wr_hold )
|
);
|
);
|
|
|
mc_mem_if u7(
|
mc_mem_if u7(
|
.clk( clk ),
|
.clk( clk_i ),
|
.rst( rst ),
|
.rst( rst_i ),
|
.mc_clk( mc_clk ),
|
.mc_clk( mc_clk_i ),
|
.mc_br( mc_br ),
|
.mc_br( mc_br_pad_i ),
|
.mc_bg( mc_bg ),
|
.mc_bg( mc_bg_pad_o ),
|
.mc_addr( mc_addr ),
|
.mc_addr( mc_addr_pad_o ),
|
.mc_data_o( mc_data_o ),
|
.mc_data_o( mc_data_pad_o ),
|
.mc_dp_o( mc_dp_o ),
|
.mc_dp_o( mc_dp_pad_o ),
|
.mc_data_oe( mc_data_oe ),
|
.mc_data_oe( mc_doe_pad_doe_o),
|
.mc_dqm( mc_dqm ),
|
.mc_dqm( mc_dqm_pad_o ),
|
.mc_oe_( mc_oe_ ),
|
.mc_oe_( mc_oe_pad_o_ ),
|
.mc_we_( mc_we_ ),
|
.mc_we_( mc_we_pad_o_ ),
|
.mc_cas_( mc_cas_ ),
|
.mc_cas_( mc_cas_pad_o_ ),
|
.mc_ras_( mc_ras_ ),
|
.mc_ras_( mc_ras_pad_o_ ),
|
.mc_cke_( mc_cke_ ),
|
.mc_cke_( mc_cke_pad_o_ ),
|
.mc_cs_( mc_cs_ ),
|
.mc_cs_( mc_cs_pad_o_ ),
|
.mc_adsc_( mc_adsc_ ),
|
.mc_adsc_( mc_adsc_pad_o_ ),
|
.mc_adv_( mc_adv_ ),
|
.mc_adv_( mc_adv_pad_o_ ),
|
.mc_br_r( mc_br_r ),
|
.mc_br_r( mc_br_r ),
|
.mc_bg_d( mc_bg_d ),
|
.mc_bg_d( mc_bg_d ),
|
.mc_data_od( mc_data_od ),
|
.mc_data_od( mc_data_od ),
|
.mc_dp_od( mc_dp_od ),
|
.mc_dp_od( mc_dp_od ),
|
.mc_addr_d( mc_addr_d ),
|
.mc_addr_d( mc_addr_d ),
|
.mc_ack( mc_ack ),
|
.mc_ack( mc_ack_pad_i ),
|
.we_( we_ ),
|
.we_( we_ ),
|
.ras_( ras_ ),
|
.ras_( ras_ ),
|
.cas_( cas_ ),
|
.cas_( cas_ ),
|
.cke_( cke_ ),
|
.cke_( cke_ ),
|
.mc_adsc_d( mc_adsc_d ),
|
.mc_adsc_d( mc_adsc_d ),
|
| Line 481... |
Line 490... |
.lmr_sel( lmr_sel ),
|
.lmr_sel( lmr_sel ),
|
.spec_req_cs( spec_req_cs ),
|
.spec_req_cs( spec_req_cs ),
|
.cs( cs ),
|
.cs( cs ),
|
.data_oe( data_oe ),
|
.data_oe( data_oe ),
|
.susp_sel( susp_sel ),
|
.susp_sel( susp_sel ),
|
.mc_c_oe( mc_c_oe ),
|
.mc_c_oe( mc_coe_pad_coe_o),
|
.mc_ack_r( mc_ack_r ),
|
.mc_ack_r( mc_ack_r ),
|
.oe_( oe_ ),
|
.oe_( oe_ ),
|
.wb_stb_i( wb_stb_i ),
|
.wb_stb_i( wb_stb_i ),
|
.wb_sel_i( wb_sel_i ),
|
.wb_sel_i( wb_sel_i ),
|
.wb_cycle( wb_cycle ),
|
.wb_cycle( wb_cycle ),
|
