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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: mc_wb_if.v,v 1.3 2001-09-24 00:38:21 rudi Exp $
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// $Id: mc_wb_if.v,v 1.4 2001-11-29 02:16:28 rudi Exp $
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//
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//
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// $Date: 2001-09-24 00:38:21 $
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// $Date: 2001-11-29 02:16:28 $
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// $Revision: 1.3 $
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// $Revision: 1.4 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2001/09/24 00:38:21 rudi
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//
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// Changed Reset to be active high and async.
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//
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// Revision 1.2 2001/08/10 08:16:21 rudi
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// Revision 1.2 2001/08/10 08:16:21 rudi
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//
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//
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// - Changed IO names to be more clear.
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// - Changed IO names to be more clear.
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// - Uniquifyed define names to be core specific.
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// - Uniquifyed define names to be core specific.
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// - Removed "Refresh Early" configuration
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// - Removed "Refresh Early" configuration
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// 2) Fixed several minor bugs
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// 2) Fixed several minor bugs
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//
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//
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// Revision 1.3 2001/06/12 15:19:49 rudi
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// Revision 1.3 2001/06/12 15:19:49 rudi
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//
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//
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//
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//
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// Minor changes after running lint, and a small bug fix reading csr and ba_mask registers.
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// Minor changes after running lint, and a small bug
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// fix reading csr and ba_mask registers.
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//
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//
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// Revision 1.2 2001/06/03 11:37:17 rudi
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// Revision 1.2 2001/06/03 11:37:17 rudi
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//
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//
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//
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//
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// 1) Fixed Chip Select Mask Register
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// 1) Fixed Chip Select Mask Register
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`include "mc_defines.v"
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`include "mc_defines.v"
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module mc_wb_if(clk, rst,
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module mc_wb_if(clk, rst,
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wb_addr_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_err, wb_ack_o,
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wb_addr_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_err, wb_ack_o,
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wb_read_go, wb_write_go,
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wb_read_go, wb_write_go,
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wb_first, wb_wait, mem_ack, wr_hold);
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wb_first, wb_wait, mem_ack, wr_hold,
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err, par_err, wp_err,
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wb_data_o, mem_dout, rf_dout);
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input clk, rst;
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input clk, rst;
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input [31:0] wb_addr_i;
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input [31:0] wb_addr_i;
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input wb_cyc_i;
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input wb_cyc_i;
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input wb_stb_i;
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input wb_stb_i;
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input wb_we_i;
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input wb_we_i;
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input wb_err;
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output wb_err;
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output wb_ack_o;
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output wb_ack_o;
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output wb_read_go;
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output wb_read_go;
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output wb_write_go;
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output wb_write_go;
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output wb_first;
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output wb_first;
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output wb_wait;
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output wb_wait;
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input mem_ack;
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input mem_ack;
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output wr_hold;
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output wr_hold;
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input err, par_err, wp_err;
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output [31:0] wb_data_o;
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input [31:0] mem_dout, rf_dout;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Local Wires and Registers
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// Local Wires and Registers
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//
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//
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wire wb_first_set;
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wire wb_first_set;
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reg wr_hold;
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reg wr_hold;
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wire rmw;
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wire rmw;
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reg rmw_r;
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reg rmw_r;
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reg rmw_en;
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reg rmw_en;
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reg wb_ack_o;
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reg wb_err;
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reg [31:0] wb_data_o;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Memory Go Logic
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// Memory Go Logic
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//
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//
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assign mem_sel = `MC_MEM_SEL;
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assign mem_sel = `MC_MEM_SEL;
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if(rst) rmw_en <= #1 1'b0;
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if(rst) rmw_en <= #1 1'b0;
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else
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else
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if(mem_ack) rmw_en <= #1 1'b1;
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if(wb_ack_o) rmw_en <= #1 1'b1;
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else
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else
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if(!wb_cyc_i) rmw_en <= #1 1'b0;
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if(!wb_cyc_i) rmw_en <= #1 1'b0;
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always @(posedge clk)
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always @(posedge clk)
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rmw_r <= #1 !wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en;
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rmw_r <= #1 !wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en;
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assign rmw = rmw_r | (!wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en);
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assign rmw = rmw_r | (!wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en);
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always @(posedge clk)
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always @(posedge clk)
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read_go_r1 <= #1 !rmw & wb_cyc_i & ((wb_stb_i & mem_sel & !wb_we_i) | read_go_r);
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read_go_r1 <= #1 !rmw & wb_cyc_i &
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((wb_stb_i & mem_sel & !wb_we_i) | read_go_r);
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always @(posedge clk)
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always @(posedge clk)
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read_go_r <= #1 read_go_r1 & wb_cyc_i;
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read_go_r <= #1 read_go_r1 & wb_cyc_i;
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assign wb_read_go = !rmw & read_go_r1 & wb_cyc_i;
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assign wb_read_go = !rmw & read_go_r1 & wb_cyc_i;
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assign wb_write_go = !rmw & write_go_r1 & wb_cyc_i &
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assign wb_write_go = !rmw & write_go_r1 & wb_cyc_i &
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((wb_we_i & wb_stb_i) | !wb_stb_i);
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((wb_we_i & wb_stb_i) | !wb_stb_i);
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assign wb_first_set = mem_sel & wb_cyc_i & wb_stb_i & !(read_go_r | write_go_r);
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assign wb_first_set = mem_sel & wb_cyc_i & wb_stb_i & !(read_go_r | write_go_r);
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assign wb_first = wb_first_set | (wb_first_r & !mem_ack & !wb_err);
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assign wb_first = wb_first_set | (wb_first_r & !wb_ack_o & !wb_err);
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if(rst) wb_first_r <= #1 1'b0;
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if(rst) wb_first_r <= #1 1'b0;
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else
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else
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if(wb_first_set) wb_first_r <= #1 1'b1;
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if(wb_first_set) wb_first_r <= #1 1'b1;
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else
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else
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if(mem_ack | wb_err) wb_first_r <= #1 1'b0;
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if(wb_ack_o | wb_err) wb_first_r <= #1 1'b0;
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always @(posedge clk)
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always @(posedge clk)
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if(wb_cyc_i & wb_stb_i) wr_hold <= #1 wb_we_i;
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if(wb_cyc_i & wb_stb_i) wr_hold <= #1 wb_we_i;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// WB Ack
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// WB Ack
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//
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//
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assign wb_ack_o = mem_ack;
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always @(posedge clk)
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wb_ack_o <= #1 `MC_MEM_SEL ? mem_ack :
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`MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_ack_o;
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always @(posedge clk)
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wb_err <= #1 wb_cyc_i & wb_stb_i & `MC_MEM_SEL &
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(par_err | err | wp_err) & !wb_err;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Memory Wait Logic
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// Memory Wait Logic
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//
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//
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assign wb_wait = wb_cyc_i & !wb_stb_i & (wb_write_go | wb_read_go);
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assign wb_wait = wb_cyc_i & !wb_stb_i & (wb_write_go | wb_read_go);
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////////////////////////////////////////////////////////////////////
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//
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// WISHBONE Data Output
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//
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always @(posedge clk)
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wb_data_o <= #1 `MC_MEM_SEL ? mem_dout : rf_dout;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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