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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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// CVS Log
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//
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//
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// $Id: mc_wb_if.v,v 1.4 2001-11-29 02:16:28 rudi Exp $
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// $Id: mc_wb_if.v,v 1.5 2001-12-11 02:47:19 rudi Exp $
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//
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//
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// $Date: 2001-11-29 02:16:28 $
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// $Date: 2001-12-11 02:47:19 $
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// $Revision: 1.4 $
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// $Revision: 1.5 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2001/11/29 02:16:28 rudi
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//
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//
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// - More Synthesis cleanup, mostly for speed
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// - Several bug fixes
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// - Changed code to avoid auto-precharge and
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// burst-terminate combinations (apparently illegal ?)
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// Now we will do a manual precharge ...
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//
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// Revision 1.3 2001/09/24 00:38:21 rudi
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// Revision 1.3 2001/09/24 00:38:21 rudi
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//
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//
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// Changed Reset to be active high and async.
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// Changed Reset to be active high and async.
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//
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//
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// Revision 1.2 2001/08/10 08:16:21 rudi
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// Revision 1.2 2001/08/10 08:16:21 rudi
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Line 159... |
else
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else
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if(wb_ack_o) rmw_en <= #1 1'b1;
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if(wb_ack_o) rmw_en <= #1 1'b1;
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else
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else
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if(!wb_cyc_i) rmw_en <= #1 1'b0;
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if(!wb_cyc_i) rmw_en <= #1 1'b0;
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always @(posedge clk)
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always @(posedge clk or posedge rst)
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rmw_r <= #1 !wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en;
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if(rst) rmw_r <= #1 1'b0;
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else rmw_r <= #1 !wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en;
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assign rmw = rmw_r | (!wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en);
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assign rmw = rmw_r | (!wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en);
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always @(posedge clk)
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always @(posedge clk or posedge rst)
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read_go_r1 <= #1 !rmw & wb_cyc_i &
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if(rst) read_go_r1 <= #1 1'b0;
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else read_go_r1 <= #1 !rmw & wb_cyc_i &
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((wb_stb_i & mem_sel & !wb_we_i) | read_go_r);
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((wb_stb_i & mem_sel & !wb_we_i) | read_go_r);
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always @(posedge clk)
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always @(posedge clk or posedge rst)
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read_go_r <= #1 read_go_r1 & wb_cyc_i;
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if(rst) read_go_r <= #1 1'b0;
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else read_go_r <= #1 read_go_r1 & wb_cyc_i;
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assign wb_read_go = !rmw & read_go_r1 & wb_cyc_i;
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assign wb_read_go = !rmw & read_go_r1 & wb_cyc_i;
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always @(posedge clk)
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always @(posedge clk or posedge rst)
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write_go_r1 <= #1 wb_cyc_i & ((wb_stb_i & mem_sel & wb_we_i) | write_go_r);
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if(rst) write_go_r1 <= #1 1'b0;
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else write_go_r1 <= #1 wb_cyc_i &
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((wb_stb_i & mem_sel & wb_we_i) | write_go_r);
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always @(posedge clk)
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always @(posedge clk or posedge rst)
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write_go_r <= #1 write_go_r1 & wb_cyc_i &
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if(rst) write_go_r <= #1 1'b0;
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else write_go_r <= #1 write_go_r1 & wb_cyc_i &
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((wb_we_i & wb_stb_i) | !wb_stb_i);
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((wb_we_i & wb_stb_i) | !wb_stb_i);
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assign wb_write_go = !rmw & write_go_r1 & wb_cyc_i &
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assign wb_write_go = !rmw & write_go_r1 & wb_cyc_i &
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((wb_we_i & wb_stb_i) | !wb_stb_i);
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((wb_we_i & wb_stb_i) | !wb_stb_i);
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Line 199... |
else
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else
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if(wb_first_set) wb_first_r <= #1 1'b1;
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if(wb_first_set) wb_first_r <= #1 1'b1;
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else
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else
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if(wb_ack_o | wb_err) wb_first_r <= #1 1'b0;
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if(wb_ack_o | wb_err) wb_first_r <= #1 1'b0;
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always @(posedge clk)
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always @(posedge clk or posedge rst)
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if(rst) wr_hold <= #1 1'b0;
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else
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if(wb_cyc_i & wb_stb_i) wr_hold <= #1 wb_we_i;
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if(wb_cyc_i & wb_stb_i) wr_hold <= #1 wb_we_i;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// WB Ack
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// WB Ack
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//
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//
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always @(posedge clk)
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always @(posedge clk or posedge rst)
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wb_ack_o <= #1 `MC_MEM_SEL ? mem_ack :
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if(rst) wb_ack_o <= #1 1'b0;
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else wb_ack_o <= #1 `MC_MEM_SEL ? mem_ack :
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`MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_ack_o;
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`MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_ack_o;
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always @(posedge clk)
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always @(posedge clk or posedge rst)
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wb_err <= #1 wb_cyc_i & wb_stb_i & `MC_MEM_SEL &
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if(rst) wb_err <= #1 1'b0;
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else wb_err <= #1 wb_cyc_i & wb_stb_i & `MC_MEM_SEL &
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(par_err | err | wp_err) & !wb_err;
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(par_err | err | wp_err) & !wb_err;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Memory Wait Logic
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// Memory Wait Logic
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