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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
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//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Rudolf Usselmann ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////
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|
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// CVS Log
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// CVS Log
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//
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//
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// $Id: mc_wb_if.v,v 1.5 2001-12-11 02:47:19 rudi Exp $
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// $Id: mc_wb_if.v,v 1.6 2002-01-21 13:08:52 rudi Exp $
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//
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//
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// $Date: 2001-12-11 02:47:19 $
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// $Date: 2002-01-21 13:08:52 $
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// $Revision: 1.5 $
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// $Revision: 1.6 $
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// $Author: rudi $
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// $Author: rudi $
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// $Locker: $
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// $Locker: $
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// $State: Exp $
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// $State: Exp $
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//
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//
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// Change History:
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// Change History:
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.5 2001/12/11 02:47:19 rudi
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//
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// - Made some changes not to expect clock during reset ...
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//
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// Revision 1.4 2001/11/29 02:16:28 rudi
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// Revision 1.4 2001/11/29 02:16:28 rudi
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//
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//
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//
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//
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// - More Synthesis cleanup, mostly for speed
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// - More Synthesis cleanup, mostly for speed
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// - Several bug fixes
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// - Several bug fixes
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// WB Ack
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// WB Ack
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//
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//
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wire wb_err_d;
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// Ack no longer asserted when wb_err is asserted
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if(rst) wb_ack_o <= #1 1'b0;
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if(rst) wb_ack_o <= #1 1'b0;
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else wb_ack_o <= #1 `MC_MEM_SEL ? mem_ack :
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else wb_ack_o <= #1 `MC_MEM_SEL ? mem_ack & !wb_err_d :
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`MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_ack_o;
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`MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_ack_o;
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assign wb_err_d = wb_cyc_i & wb_stb_i & (par_err | err | wp_err);
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if(rst) wb_err <= #1 1'b0;
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if(rst) wb_err <= #1 1'b0;
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else wb_err <= #1 wb_cyc_i & wb_stb_i & `MC_MEM_SEL &
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else wb_err <= #1 `MC_MEM_SEL & wb_err_d & !wb_err;
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(par_err | err | wp_err) & !wb_err;
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Memory Wait Logic
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// Memory Wait Logic
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//
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//
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