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//----------------------------------------------------------------------------
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// Wishbone memory_sizer core
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//
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// This file is part of the "memory_sizer" project.
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// http://www.opencores.org/cores/memory_sizer
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//
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//
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// Description: See description below (which suffices for IP core
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// specification document.)
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//
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// Copyright (C) 2001 John Clayton and OPENCORES.ORG
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//
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// This source file may be used and distributed without restriction provided
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// that this copyright statement is not removed from the file and that any
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// derivative work contains the original copyright notice and the associated
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// disclaimer.
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//
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// This source file is free software; you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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//
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// This source is distributed in the hope that it will be useful, but WITHOUT
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// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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// License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public License
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// along with this source.
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// If not, download it from http://www.opencores.org/lgpl.shtml
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//
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//-------------------------------------------------------------------------------------
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//
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// Author: John Clayton
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// Date : November 5, 2001
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// Update: 11/05/01 copied this file from rs232_syscon.v (pared down).
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// Update: 11/16/01 Continued coding efforts. Redesigned logic to include scalable
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// "byte sized barrel shifter" and byte reversal blocks (the byte
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// reversal is implemented as a function "byte_reversal").
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// Changed encoding of memory_width_i and access_width_i.
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// Implemented new counting and byte enable logic.
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// Update: 12/04/01 Realized there was a mistake in the byte enable logic.
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// Fixed it by using dat_shift to shift the byte enables.
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// Made "byte_enable_source" twice as wide.
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// Update: 12/05/01 Eliminated the "count" in favor of using "dat_shift" along
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// with new terminal_count logic, in order to fix flaws found
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// in the terminal_count signal. Fixed byte steering for
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// stores. Tested using N_PP = 4, and LOG2_N_PP = 2 and saw
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// correct operation for all sizes of store operations.
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// Update: 12/13/01 Began testing with read logic. Found byte enable problem
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// during writes. Removed "byte_dirty" bits.
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// Update: 12/14/01 Added "latch_be_source" to create byte enables for reading
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// which are based on the size of the memory (which fixed a
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// bug in reading.) The module appears to be fully working,
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// except for "big_endian" reads.
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// Update: 12/17/01 Introduced the "middle_bus" in order to decouple the
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// byte reverser from the byte steering logic, so that for
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// writes byte reversing is done first, but for reads then
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// byte reversing is done last. Introduced "latch_be_adjust"
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// to cover big endian reads -- all is now working.
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// Update: 12/17/01 Removed "middle_bus" (the two units are still decoupled!)
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// because it seemed unnecessary. This freed up Tbuffs, but
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// had no effect on resource utilization (slices). Also, the
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// maximum reported clock speed increased. Removed debug
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// port.
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// Update: 12/18/01 Added file header according to opencores recommendations.
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//
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// Description
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//-------------------------------------------------------------------------------------
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// This logic module takes care of sizing bus transfers between a small
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// microprocessor and its memory. It enables the microprocessor to
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// generate access requests for different widths (read/write BYTE, WORD and
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// DWORD, etc.) using memory which is sized independently of the accesses.
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//
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// Thus, a 32-bit microprocessor using 32-bit wide accesses can use this block
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// in order to boot from an 8-bit wide flash device. This block takes care of
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// generating the four 8-bit memory cycles that are required in order to read
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// each DWORD for alimentation of the microprocessor.
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//
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// Also, if the memory supports byte enables during a write cycle, then this
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// block "steers" a smaller data word to the appropriate location within a
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// larger memory word, and activates the appropriate byte enables so that only
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// the BYTEs which are affected by the write cycle are actually overwritten.
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//
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// Moreover, the memory_sizer block takes care of translating little-endian
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// formats into big-endian formats and vice-versa. This is accomplished by the
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// use of a single input bit "endianness_i"
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//
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// The memory_sizer block does not latch or store the parameters which it uses
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// for operation. The input signals determine its operation on an ongoing
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// basis. In fact, the only data storage present in this block is the latching
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// provided for data which must be held during multiple cycle read operations.
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// (There are also some counters, which don't count as data storage...)
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//
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// Encoding for access_width_i and memory_width_i is as follows:
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//
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// Bits Significance
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// ------ ------------
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// 0001 8-bits wide (1 byte)
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// 0010 16-bits wide (2 bytes)
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// 0100 32-bits wide (4 bytes)
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// 1000 64-bits wide (8 bytes)
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//
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// (The access_width_i and memory_width_i inputs are sized according to the
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// parameter LOG2_N_PP, but the significance is the same, using whatever
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// lsbs are present.)
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//
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// It is envisioned that a designer may include this block for flexibility.
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// If all of the memory accesses are of a single width, and the memory matches
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// that width, and there is no need for endianness translation, then the user
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// could hard-code the "memory_width_i" and "access_width_i" to correspond
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// to the same width, hard-code the "endianness_i" input to the desired value
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// and then the memory_sizer block would effectively do nothing, or very little.
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// Most of its size and resources would be optimized out of the design at
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// compile time. The dat_shift counter and read-storage latches would not be
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// used, and so they would not even be synthesized.
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//
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// On the other hand, if the memory in the SOC (system on a chip) comprises
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// various width devices, then the decode logic which selects the blocks of
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// memory is ORed (for each like-sized block) and then concatenated in the
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// proper order to generate a dynamic "mem_width_i" signal to the
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// memory_sizer, so that the different size accesses are accomodated. The
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// processor side, meanwhile (being "access_width_i"), could still be
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// hard-wired to a given width, or be connected so that different width loads
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// and stores are generated as needed.
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//
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// This block may generate exceptions to the processor, in the case of a write
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// request, for example, to store a BYTE into a DWORD wide memory which doesn't
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// support the use of byte enables. Although this could be done by reading the
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// wider memory and masking in the correct BYTE, followed by storing the
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// results back into the memory, this was deemed too complex a task for this
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// block. Responsibility for such operations, if desired, would devolve upon
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// the microprocessor itself. Support of byte enables is indicated by a "1" on
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// the "memory_has_be_i" line.
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//
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// The clock used by memory_sizer is not limited to the speed of the clock used
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// by the microprocessor. Since the memory_sizer contains only combinational
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// logic, simple counters and some possible latches, it might run much faster
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// than the microprocessor. In that case, generate two clocks which are
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// synchronous: one for the processor, and another for memory_sizer.
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// The memory_sizer clock could be 2x, 4x or even 8x that of the processor.
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// In this way, the memory_sizer block can complete multiple memory read cycles
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// in the same time as a single processor cycle -- assuming the memory is fast
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// enough to support it -- and thereby the memory latency can be reduced.
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//
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// The memory_sizer block is not responsible for implementing wait states for
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// the memory, especially since the number of wait states required can vary
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// for each type and width of memory used. Instead, there is an "access_ack_o"
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// signal to indicate completion of the entire requested memory access to the
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// processor. On the memory side, there is "memory_ack_i" used to indicate to
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// the memory_sizer block that the memory has completed the current cycle in
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// progress. Therefore, in order to implement wait states, the memory sytem
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// address decoder logic should generate the "memory_ack_i" signal based on the
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// different types of memory present within the system, which can also be
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// programmable. A parameterized watchdog timer inside of the memory sizer block
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// indicates when "memory_ack_i" has not been asserted in a reasonable number
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// of clock cycles. When this occurs, an exception is raised. The timer
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// is started when "sel_i" is active (high). sel_i must remain active
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// until the access is completed, otherwise the timer will reset and the
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// access is aborted. If you don't want to use the watchdog portion of this
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// block then simply don't connect the exception_watchdog_o line, and the watchdog
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// timer will be optimized out of the logic.
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//
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// If desired, registers can be placed on the memory side of the block. They
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// are treated just like memory of a given width, although access requests for
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// misaligned writes, or writes which are smaller than the size of the registers,
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// should generate exceptions, unless the registers support byte enables.
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//
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// Addresses are always assumed to be byte addresses in this unit, since the
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// smallest granularity of data used in it is the BYTE. Also, the data bus
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// size used must be a multiple of 8 bits, for the same reason.
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//
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//-------------------------------------------------------------------------------------
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`define BYTE_SIZE 8 // Number of bits in one byte
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module memory_sizer (
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clk_i,
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reset_i,
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sel_i,
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memory_ack_i,
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memory_has_be_i,
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memory_width_i,
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access_width_i,
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access_big_endian_i,
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adr_i,
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we_i,
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dat_io,
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memory_dat_io,
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memory_adr_o, // Same width as adr_i (only lsbs are modified)
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memory_we_o,
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memory_be_o,
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access_ack_o,
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exception_be_o,
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exception_watchdog_o
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);
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// Parameters
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// The timer value can be from [0 to (2^WATCHDOG_TIMER_BITS_PP)-1] inclusive.
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parameter N_PP = 4; // number of bytes in data bus
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parameter LOG2_N_PP = 2; // log base 2 of data bus size (bytes)
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parameter ADR_BITS_PP = 32; // # of bits in adr buses
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parameter WATCHDOG_TIMER_VALUE_PP = 12; // # of sys_clks before ack expected
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parameter WATCHDOG_TIMER_BITS_PP = 4; // # of bits needed for timer
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// I/O declarations
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input clk_i; // Memory sub-system clock input
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input reset_i; // Reset signal for this module
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input sel_i; // Enables watchdog timer, activates memory_sizer
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input memory_ack_i; // Ack from memory (delay for wait states)
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input memory_has_be_i; // Indicates memory at current address has byte enables
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input [LOG2_N_PP:0] memory_width_i; // Width code of memory
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input [LOG2_N_PP:0] access_width_i; // Width code of access request
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input access_big_endian_i; // 0=little endian, 1=big endian
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input [ADR_BITS_PP-1:0] adr_i; // Address bus input
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input we_i; // type of access
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inout [`BYTE_SIZE*N_PP-1:0] dat_io; // processor data bus
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inout [`BYTE_SIZE*N_PP-1:0] memory_dat_io; // data bus to memory
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output [ADR_BITS_PP-1:0] memory_adr_o; // address bus to memory
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output memory_we_o; // we to memory
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output [N_PP-1:0] memory_be_o; // byte enables to memory
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output access_ack_o; // shows that access is completed
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output exception_be_o; // exception for write to non-byte-enabled memory
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output exception_watchdog_o; // exception for memory_ack_i watch dog timeout
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// Internal signal declarations
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wire [2*N_PP-1:0] memory_be_source; // Unshifted byte enables for writing
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wire [2*N_PP-1:0] latch_be_source; // Unshifted byte enables for reading
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wire [N_PP-1:0] latch_be; // "latch_be" is like "memory_be_o"
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wire [N_PP-1:0] latch_be_lil_endian; // but used internally for reads.
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wire [N_PP-1:0] latch_be_big_endian;
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wire [LOG2_N_PP-1:0] latch_be_adjust;
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wire [LOG2_N_PP+1:0] dat_shift_next; // Next dat_shift value (extra bit
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// is for terminal count compare.)
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wire [LOG2_N_PP-1:0] alignment; // shows aligment of access
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wire terminal_count; // signifies last store cycle
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wire [`BYTE_SIZE*N_PP-1:0] steer_dat_i; // data input to byte steering logic
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wire [`BYTE_SIZE*N_PP-1:0] revrs_dat_i; // data input to byte reversing logic
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reg [LOG2_N_PP-1:0] byte_mux_select; // selects which bytes to transfer
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reg [LOG2_N_PP:0] dat_shift; // shift amt. for data and byte enables
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reg [`BYTE_SIZE*N_PP-1:0] revrs_dat_o; // data out from byte reversing logic
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reg [`BYTE_SIZE*N_PP-1:0] steer_dat_o; // data out from byte steering logic
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reg [`BYTE_SIZE*N_PP-1:0] read_dat; // read data (after latch bypassing)
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reg [`BYTE_SIZE*N_PP-1:0] latched_read_dat; // read values before latch bypass
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reg [WATCHDOG_TIMER_BITS_PP-1:0] watchdog_count;
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//--------------------------------------------------------------------------
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// Instantiations
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//--------------------------------------------------------------------------
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//--------------------------------------------------------------------------
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// Functions & Tasks
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//--------------------------------------------------------------------------
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function [`BYTE_SIZE*N_PP-1:0] byte_reversal;
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input [`BYTE_SIZE*N_PP-1:0] din;
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integer k;
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begin
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for (k=0; k<N_PP; k=k+1)
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byte_reversal[`BYTE_SIZE*(N_PP-k)-1:`BYTE_SIZE*(N_PP-k-1)]
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<= din[`BYTE_SIZE*(k+1)-1:`BYTE_SIZE*k];
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end
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endfunction
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//--------------------------------------------------------------------------
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// Module code
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//--------------------------------------------------------------------------
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// Mask off the address bits that don't matter for alignment
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assign alignment = (memory_width_i - 1) & adr_i[LOG2_N_PP-1:0];
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// Setting up the basic (alignment shifted) byte enables
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assign memory_be_source = ((1<<access_width_i)-1);
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assign latch_be_source = ((1<<memory_width_i)-1);
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// Assigning the byte enables and latch enables
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assign memory_be_o = we_i?((memory_be_source << alignment) >> dat_shift)
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:{N_PP{1'b1}};
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// (memory byte enables are all high for reads!)
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// For big_endian reads, the latch byte enables (and indeed the data also)
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// are shifted using a special mapping, which causes the data to appear at
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// the opposite end of the "read_data" bus.
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assign latch_be_lil_endian = ((latch_be_source << dat_shift) >> alignment);
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assign latch_be_adjust = ~(access_width_i[LOG2_N_PP-1:0]-1);
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assign latch_be_big_endian = latch_be_lil_endian << latch_be_adjust;
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assign latch_be = (access_big_endian_i)?latch_be_big_endian
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:latch_be_lil_endian;
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// Exceptions
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assign exception_be_o = (alignment != 0) && ~memory_has_be_i;
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assign exception_watchdog_o = (watchdog_count == WATCHDOG_TIMER_VALUE_PP);
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// Pass signals to memory
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assign memory_we_o = we_i;
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// Enable the data bus outputs in each direction
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assign dat_io = (sel_i && ~we_i)?revrs_dat_o:{`BYTE_SIZE*N_PP{1'bZ}};
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assign memory_dat_io = (sel_i && we_i)?steer_dat_o:{`BYTE_SIZE*N_PP{1'bZ}};
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// Decide which bus supplies the byte reversing logic
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// (One could just use a single mux here instead of the tri-state buffers.
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// in fact, the synthesis tool might decide to change the tri-state buffers
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// into simple 2:1 muxes...)
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assign revrs_dat_i = (~we_i)?read_dat:{`BYTE_SIZE*N_PP{1'bZ}};
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assign revrs_dat_i = (we_i)?dat_io:{`BYTE_SIZE*N_PP{1'bZ}};
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// Decide which bus supplies the byte steering logic
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// (One could just use a single mux here instead of the tri-state buffers.
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// in fact, the synthesis tool might decide to change the tri-state buffers
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// into simple 2:1 muxes...)
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assign steer_dat_i = (~we_i)?memory_dat_io:{`BYTE_SIZE*N_PP{1'bZ}};
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assign steer_dat_i = (we_i)?revrs_dat_o:{`BYTE_SIZE*N_PP{1'bZ}};
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// This logic latches the data bytes which are read during the first cycles
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// of an access. During the final cycle of the access, then "terminal_count"
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// is asserted by the counting logic, which causes the latches which are
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// "non-dirty" (i.e. which do not yet contain data) to be bypassed by muxes.
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// This means that for single cycle accesses, the data will flow directly
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// around the latches and an extra clock cycle will not be needed in order
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// to latch the data...
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always @(posedge clk_i)
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begin: BYTE_LATCHES
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integer i;
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if (reset_i || terminal_count || ~sel_i)
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begin
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latched_read_dat <= 0;
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end
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else if (sel_i && ~we_i && memory_ack_i)
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begin
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for (i=0;i<N_PP;i=i+1)
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begin
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if (latch_be[i]) latched_read_dat[`BYTE_SIZE*(i+1)-1:`BYTE_SIZE*i]
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<= steer_dat_o[`BYTE_SIZE*(i+1)-1:`BYTE_SIZE*i];
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end
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end
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end
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// This part handles the bypass muxes
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always @(
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terminal_count or
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latch_be or
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steer_dat_o or
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latched_read_dat
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)
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begin: LATCH_BYPASS
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integer j;
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for (j=0;j<N_PP;j=j+1)
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begin
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if (terminal_count && latch_be[j])
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read_dat[`BYTE_SIZE*(j+1)-1:`BYTE_SIZE*j]
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<= steer_dat_o[`BYTE_SIZE*(j+1)-1:`BYTE_SIZE*j];
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else read_dat[`BYTE_SIZE*(j+1)-1:`BYTE_SIZE*j]
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<= latched_read_dat[`BYTE_SIZE*(j+1)-1:`BYTE_SIZE*j];
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end
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end
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// Byte reversal logic (reused for both reads and writes)
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always @(
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revrs_dat_i or
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access_big_endian_i
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)
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begin
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// Reverse the bytes of the data bus, if needed
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if (access_big_endian_i) revrs_dat_o <= byte_reversal(revrs_dat_i);
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else revrs_dat_o <= revrs_dat_i;
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end
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// Steering logic (reused for both reads and writes)
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always @(
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steer_dat_i or
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dat_shift or
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alignment or
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we_i or
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access_width_i or
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access_big_endian_i
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)
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begin
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// If bytes are reversed, an extra "bit inversion mask" is applied
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// to reflect a new mapping which is correct for reversed bytes.
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if (access_big_endian_i && we_i)
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byte_mux_select <= (dat_shift[LOG2_N_PP-1:0] ^ ~(access_width_i-1))
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- alignment;
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else if (~access_big_endian_i && we_i)
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byte_mux_select <= dat_shift - alignment;
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// For reads, negate the shift amount
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else if (access_big_endian_i && ~we_i)
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byte_mux_select <= alignment
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- (dat_shift[LOG2_N_PP-1:0] ^ ~(access_width_i-1));
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else if (~access_big_endian_i && ~we_i)
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byte_mux_select <= alignment - dat_shift;
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// Rotate the data bus (byte-sized barrel shifter!)
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steer_dat_o <= (
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(steer_dat_i >> `BYTE_SIZE*byte_mux_select)
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|(steer_dat_i << `BYTE_SIZE*(N_PP-byte_mux_select))
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);
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end
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// This is the counting logic.
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// It is implemented using "count_next" in order to detect when
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// the last cycle is being performed, which is when the "next" count
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// equals or exceeds the total size of the access requested in bytes.
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// (Using the "next" approach avoids issues relating to different
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// memory sizes!)
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always @(posedge clk_i)
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begin
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if (reset_i || terminal_count || ~sel_i) dat_shift <= 0;
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else if (memory_ack_i) dat_shift <= dat_shift_next;
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end
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assign dat_shift_next = dat_shift + memory_width_i;
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assign terminal_count = (dat_shift_next >= (access_width_i + alignment));
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assign memory_adr_o = adr_i + dat_shift;
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assign access_ack_o = terminal_count && sel_i;
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// This is the watchdog timer
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// It runs whenever the memory_sizer is selected for an access, and the
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// memory has not yet responded with an ack signal.
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always @(posedge clk_i)
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begin
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if (reset_i || ~sel_i || memory_ack_i) watchdog_count <= 0;
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else if (~exception_watchdog_o) watchdog_count <= watchdog_count + 1;
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end
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endmodule
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