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?rev2line? |
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The encoding info is scattered in the source I'm gonna organize it all soon.
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Registers:
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0000: $SP - Stack Pointer
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0001: $GP - Global Pointer
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0010: $RA - Return Address
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0011: $SYS - System
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0100: $R0 - General Purpose Registers
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0101: $R1
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0110: $R2
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0111: $R3
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1000: $R4
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1001: $R5
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1010: $R6
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1011: $R7
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1100: $T0 - Temporary Registers
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1101: $T1
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1110: $T2
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1111: $T3
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MicroRISC II Instruction Set
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Arithmetic:
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ADD
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SUB
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MUL(U) // Optional / By default it is included
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DIV(U) // Optional
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MOD(U) // Optional
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SHR
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SHL
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ROR
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ROL
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PCNT // Population One Count
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PCNTZ // Population Zero Count
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PCNTC // Population Change Count
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RND // Random Number Generator
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Arguments: reg,reg,reg
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Arguments: reg,reg,imm16
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0100:
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| OP(4) | ALUOP(4) | REGD(4) | REGA(4) | REGB(4) | VOID(12) |
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0101:
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| OP(4) | ALUOP(4) | REGD(4) | REGA(4) | IMM(16) |
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Logic:
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OR
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AND
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XOR
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NOT
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Arguments: reg,reg,reg
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0010:
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| OP(4) | LOGICOP(2) | VOID(2) | REGD(4) | REGA(4) | REGB(4) | VOID(12) |
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0011:
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| OP(4) | LOGICOP(2) | HIGH/LOW(1) | VOID(1) | REGD(4) | REGA(4) | VOID(16) |
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Memory:
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LB/LW/LD(S)
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SB/SW/SD
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Arguments: reg,[reg+imm16]
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0001:
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| OP(4) | STORE/LOAD(1) | SIGNED(1) | SIZE(2) | REGD(4) | REGA(4) | IMM(16) |
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Branch:
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J(L) 1000
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JR(L) 1001
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BEQ(L) 1010
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BNE(L) 1011
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BZ(L) 1100
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BNZ(L) 1101
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BC(L) 1110
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BNC(L) 1111
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| OP(4) | REGD(4) | REGA(4) | REGB(4) | IMM(16) |
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BLT(L)
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BLTU(L)
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BNL(L)
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BNLU(L)
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BGT(L)
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BGTU(L)
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BNG(L)
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BNGU(L)
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0111:
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| OP(4) | BranchOP(4) | REGD(4) | REGA(4) | REGB(4) | VOID(4) | IMM(8) |
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Interupts/Special:
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NOP // No Operation
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LLW imm16 // Load Low Word // Erases register and places 16bit value
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LHW imm16 // Load High Word // Erases register and places the 16bit value
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SIV reg // Set Interupt Vector
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GIV reg // Get Interupt Vector
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THROW reg // Throw and load soft cause(16 bits)
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THROW imm16 // Throw
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CAUSE reg // Get Cause(32 bits)
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IRET reg // Interupt Return
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GPRSR reg // Get Program Restore State Register(Carry,etc.)
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SPRSR reg // Set Program Restore State Register
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SWMC // Switch Microcode Size(16bit/32bit)
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0000:
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| OP(4) | SOP(4) | REGD(4) | REGA(4) | IMM(16) |
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