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-- $Id: input.vhdl,v 1.1.1.1 2005-12-06 02:47:46 arif_endro Exp $
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-- $Id: input.vhdl,v 1.2 2005-12-23 04:27:00 arif_endro Exp $
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Input
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-- Title : Input
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-- Project : Mini AES 128
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-- Project : Mini AES 128
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : input.vhdl
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-- File : input.vhdl
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use std_developerskit.std_iopak.all; -- Function From_HexString
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use std_developerskit.std_iopak.all; -- Function From_HexString
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entity input is
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entity input is
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port (
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port (
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clock : out std_logic;
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clock : out std_logic;
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clear : out std_logic;
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load : out std_logic;
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done : in std_logic;
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done : in std_logic;
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test_iteration : out integer;
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test_iteration : out integer;
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data_i : out std_logic_vector (127 downto 000);
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key_i_byte : out std_logic_vector (007 downto 000);
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cipher_o : out std_logic_vector (127 downto 000);
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data_i_byte : out std_logic_vector (007 downto 000);
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key_i : out std_logic_vector (127 downto 000)
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cipher_o_byte : out std_logic_vector (007 downto 000)
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);
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);
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end input;
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end input;
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architecture test_bench of input is
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architecture test_bench of input is
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--
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--
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file in_file_ptr : text open read_mode is "../data/ecb_tbl.txt";
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file in_file_ptr : text open read_mode is "../data/ecb_tbl.txt";
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--
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--
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signal clock_int : std_logic := '0';
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signal clock_int : std_logic := '0';
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signal ct : std_logic_vector (127 downto 000);
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signal pt : std_logic_vector (127 downto 000);
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signal ky : std_logic_vector (127 downto 000);
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--
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--
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begin
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begin
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--
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--
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clock_int <= not(clock_int) after 1 ns;
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clock_int <= not(clock_int) after 1 ns;
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clock <= clock_int;
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clock <= clock_int;
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read(in_line, plain_text);
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read(in_line, plain_text);
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readline(in_file_ptr, in_line);
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readline(in_file_ptr, in_line);
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read(in_line, junk_cipher_text);
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read(in_line, junk_cipher_text);
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read(in_line, cipher_text);
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read(in_line, cipher_text);
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--
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--
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ky <= to_StdLogicVector(From_HexString(key( 01 to 32)));
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pt <= to_StdLogicVector(From_HexString(plain_text( 01 to 32 )));
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ct <= to_StdLogicVector(From_HexString(cipher_text( 01 to 32 )));
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--
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for a in 1 to key'length/2 loop
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wait until rising_edge(clock_int);
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wait until rising_edge(clock_int);
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key_i <= to_StdLogicVector(From_HexString(key( 01 to 32)));
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key_i_byte <= to_StdLogicVector(From_HexString(key(2*a-1 to 2*a)));
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data_i <= to_StdLogicVector(From_HexString(plain_text( 01 to 32 )));
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data_i_byte <= to_StdLogicVector(From_HexString(plain_text(2*a-1 to 2*a)));
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cipher_o <= to_StdLogicVector(From_HexString(cipher_text( 01 to 32 )));
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cipher_o_byte <= to_StdLogicVector(From_HexString(cipher_text(2*a-1 to 2*a)));
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load <= '1';
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test_iteration <= test;
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test_iteration <= test;
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end loop;
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--
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--
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clear <= '1';
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wait until rising_edge(clock_int);
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wait until rising_edge(clock_int);
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clear <= '0';
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load <= '0';
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wait until rising_edge(done);
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--
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wait until falling_edge(done);
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wait until rising_edge(clock_int);
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wait until rising_edge(clock_int);
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--
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--
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end loop;
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end loop;
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wait;
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wait;
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end process;
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end process;
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