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-- $Id: output.vhdl,v 1.1.1.1 2005-12-06 02:47:47 arif_endro Exp $
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-- $Id: output.vhdl,v 1.2 2005-12-23 04:27:00 arif_endro Exp $
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Output
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-- Title : Output
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-- Project : Mini AES 128
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-- Project : Mini AES 128
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : output.vhdl
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-- File : output.vhdl
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use std.textio.all;
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use std.textio.all;
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entity output is
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entity output is
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port (
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port (
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clock : in std_logic;
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clock : in std_logic;
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clear : in std_logic;
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load : in std_logic;
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enc : in std_logic;
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enc : in std_logic;
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done : in std_logic;
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done : in std_logic;
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test_iteration : in integer;
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test_iteration : in integer;
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verifier : in std_logic_vector (127 downto 000);
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verifier : in std_logic_vector (007 downto 000);
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data_o : in std_logic_vector (127 downto 000)
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data_o : in std_logic_vector (007 downto 000)
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);
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);
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end output;
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end output;
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architecture test_bench of output is
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architecture test_bench of output is
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file out_enc_file_ptr : text open write_mode is "ecb_tbl_result_enc.txt";
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file out_enc_file_ptr : text open write_mode is "ecb_tbl_result_enc.txt";
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file out_dec_file_ptr : text open write_mode is "ecb_tbl_result_dec.txt";
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file out_dec_file_ptr : text open write_mode is "ecb_tbl_result_dec.txt";
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signal failed : integer := 0;
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signal failed : integer := 0;
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signal passed : integer := 0;
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signal passed : integer := 0;
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type fifo16x8 is array (0 to 15) of std_logic_vector (7 downto 0);
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signal fifo_verifier : fifo16x8 :=
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(
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B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
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B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
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B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000",
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B"0000_0000", B"0000_0000", B"0000_0000", B"0000_0000"
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);
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signal counter : integer range 0 to 15 := 0;
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signal current_verifier : std_logic_vector (7 downto 0);
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begin
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process(clock, clear)
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begin
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if (clear = '1') then
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counter <= 0;
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elsif (clock = '1' and clock'event) then
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if (done = '0') then
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counter <= 0;
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elsif (counter < 15 ) then
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counter <= counter + 1;
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else
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counter <= 0;
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end if;
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end if;
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end process;
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current_verifier <= fifo_verifier(counter);
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process(clock, clear)
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begin
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begin
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if (clear = '1') then
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fifo_verifier <= (others => ( others => '0'));
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elsif(clock = '1' and clock'event) then
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if (load = '1') then
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fifo_verifier <= (fifo_verifier (1 to 15) & verifier);
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end if;
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end if;
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end process;
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process (clock)
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process (clock)
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variable out_line : line;
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variable out_line : line;
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begin
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begin
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if (clock = '1' and clock'event) then
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if (clock = '1' and clock'event) then
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if (done = '1') then
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if (done = '1') then
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write(out_line, string'("Test ====> "));
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write(out_line, string'("Test ====> "));
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write(out_line, test_iteration);
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write(out_line, test_iteration);
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write(out_line, string'(" byte "));
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write(out_line, counter);
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if ( enc = '0') then
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if ( enc = '0') then
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writeline(out_enc_file_ptr, out_line);
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writeline(out_enc_file_ptr, out_line);
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else
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else
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writeline(out_dec_file_ptr, out_line);
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writeline(out_dec_file_ptr, out_line);
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end if;
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end if;
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write(out_line, string'("Expected : "));
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write(out_line, string'("Expected : "));
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write(out_line, verifier);
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write(out_line, current_verifier);
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if ( enc = '0') then
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if ( enc = '0') then
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writeline(out_enc_file_ptr, out_line);
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writeline(out_enc_file_ptr, out_line);
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else
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else
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writeline(out_dec_file_ptr, out_line);
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writeline(out_dec_file_ptr, out_line);
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end if;
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end if;
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writeline(out_enc_file_ptr, out_line);
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writeline(out_enc_file_ptr, out_line);
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else
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else
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writeline(out_dec_file_ptr, out_line);
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writeline(out_dec_file_ptr, out_line);
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end if;
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end if;
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write(out_line, string'("Status : "));
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write(out_line, string'("Status : "));
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if (verifier = data_o ) then
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if (current_verifier = data_o ) then
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write (out_line, string'("OK"));
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write (out_line, string'("OK"));
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passed <= passed + 1;
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passed <= passed + 1;
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else
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else
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write (out_line, string'("FAILED"));
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write (out_line, string'("FAILED"));
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failed <= failed + 1;
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failed <= failed + 1;
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