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[/] [mini_aes/] [trunk/] [source/] [bram_block_a.vhdl] - Diff between revs 12 and 15

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-- Synthesizers: ISE Xilinx 6.3i
 
-- Synthesizers: ISE Xilinx 6.3i
 
-- Target      : 
-- Target      : 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- Description : First block RAM used in AES implementation.
 
-- Description : First block RAM used in AES implementation.
 
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
 
-- Copyright (C) 2005 Arif E. Nugroho
 
-- Copyright (C) 2005 Arif Endro Nugroho
 
-- This VHDL design file is an open design; you can redistribute it and/or
 
 
 
-- modify it and/or implement it after contacting the author
 
 
 
-------------------------------------------------------------------------------
 
 
 
-------------------------------------------------------------------------------
 
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-- 
-- 
--         THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
 
--         THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
 
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
 
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
 
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
 
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE

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