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-- $Id: mini_aes.vhdl,v 1.1.1.1 2005-12-06 02:48:33 arif_endro Exp $
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-- $Id: mini_aes.vhdl,v 1.2 2005-12-23 04:21:39 arif_endro Exp $
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Title : Mini AES 128
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-- Title : Mini AES 128
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-- Project : Mini AES 128
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-- Project : Mini AES 128
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : mini_aes.vhdl
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-- File : mini_aes.vhdl
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Line 45... |
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entity mini_aes is
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entity mini_aes is
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port (
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port (
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clock : in std_logic;
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clock : in std_logic;
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clear : in std_logic;
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clear : in std_logic;
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load_i : in std_logic;
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enc : in std_logic; -- active low (e.g. 0 = encrypt, 1 = decrypt)
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enc : in std_logic; -- active low (e.g. 0 = encrypt, 1 = decrypt)
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key_i : in std_logic_vector (127 downto 00);
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key_i : in std_logic_vector (7 downto 0);
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data_i : in std_logic_vector (127 downto 00);
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data_i : in std_logic_vector (7 downto 0);
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data_o : out std_logic_vector (127 downto 00);
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data_o : out std_logic_vector (7 downto 0);
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done_o : out std_logic
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done_o : out std_logic
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);
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);
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end mini_aes;
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end mini_aes;
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architecture data_flow of mini_aes is
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architecture data_flow of mini_aes is
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component io_interface
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port (
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clock : in std_logic;
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clear : in std_logic;
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load_i : in std_logic;
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load_i_int : out std_logic;
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data_i : in std_logic_vector (7 downto 0);
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key_i : in std_logic_vector (7 downto 0);
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data_o : out std_logic_vector (7 downto 0);
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data_o_int : in std_logic_vector (127 downto 000);
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data_i_int : out std_logic_vector (127 downto 000);
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key_i_int : out std_logic_vector (127 downto 000);
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done_o_int : in std_logic;
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done_o : out std_logic
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);
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end component;
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component bram_block_a
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component bram_block_a
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port (
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port (
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clk_a_i : in std_logic;
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clk_a_i : in std_logic;
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en_a_i : in std_logic;
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en_a_i : in std_logic;
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we_a_i : in std_logic;
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we_a_i : in std_logic;
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| Line 198... |
Line 216... |
signal key_counter_up : integer range 0 to 43;
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signal key_counter_up : integer range 0 to 43;
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signal key_counter_down : integer range 0 to 43;
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signal key_counter_down : integer range 0 to 43;
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signal done : std_logic := '0';
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signal done : std_logic := '0';
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signal done_decrypt : std_logic := '0';
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signal done_decrypt : std_logic := '0';
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signal counter1bit : std_logic := '0';
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signal counter1bit : std_logic := '0';
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signal done_o_int : std_logic := '0';
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signal data_i_int : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );
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signal data_o_int : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );
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signal key_i_int : std_logic_vector (127 downto 000) := ( X"00000000_00000000_00000000_00000000" );
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signal load : std_logic := '0';
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signal load : std_logic := '0';
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signal load_io : std_logic := '0';
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signal di_0_i : std_logic_vector (007 downto 000);
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signal di_0_i : std_logic_vector (007 downto 000);
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signal di_1_i : std_logic_vector (007 downto 000);
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signal di_1_i : std_logic_vector (007 downto 000);
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signal di_2_i : std_logic_vector (007 downto 000);
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signal di_2_i : std_logic_vector (007 downto 000);
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signal di_3_i : std_logic_vector (007 downto 000);
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signal di_3_i : std_logic_vector (007 downto 000);
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signal do_0_o : std_logic_vector (007 downto 000);
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signal do_0_o : std_logic_vector (007 downto 000);
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Line 265... |
signal do_a_1_o : std_logic_vector (07 downto 00);
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signal do_a_1_o : std_logic_vector (07 downto 00);
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signal do_a_2_o : std_logic_vector (07 downto 00);
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signal do_a_2_o : std_logic_vector (07 downto 00);
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signal do_b_1_o : std_logic_vector (07 downto 00);
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signal do_b_1_o : std_logic_vector (07 downto 00);
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signal do_b_2_o : std_logic_vector (07 downto 00);
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signal do_b_2_o : std_logic_vector (07 downto 00);
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--signal data_i : std_logic_vector (127 downto 000) :=
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--signal data_i_int : std_logic_vector (127 downto 000) :=
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--( X"3243F6A8_885A308D_313198A2_E0370734" ); -- PT 0
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--( X"3243F6A8_885A308D_313198A2_E0370734" ); -- PT 0
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--( X"00112233_44556677_8899AABB_CCDDEEFF" ); -- PT 1
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--( X"00112233_44556677_8899AABB_CCDDEEFF" ); -- PT 1
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--( X"3925841D_02DC09FB_DC118597_196A0B32" ); -- CT 0
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--( X"3925841D_02DC09FB_DC118597_196A0B32" ); -- CT 0
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--( X"69C4E0D8_6A7B0430_D8CDB780_70B4C55A" ); -- CT 1
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--( X"69C4E0D8_6A7B0430_D8CDB780_70B4C55A" ); -- CT 1
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--signal key_i : std_logic_vector (127 downto 000) :=
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--signal key_i : std_logic_vector (127 downto 000) :=
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Line 283... |
en_a_i <= VCC;
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en_a_i <= VCC;
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en_b_i <= VCC;
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en_b_i <= VCC;
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we_a_i <= GND;
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we_a_i <= GND;
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we_b_i <= GND;
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we_b_i <= GND;
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done_o <= done_decrypt;
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done_o_int <= done_decrypt;
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my_io : io_interface
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port map (
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clock => clock,
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clear => clear,
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load_i => load_i,
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load_i_int => load_io,
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data_i => data_i,
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key_i => key_i,
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data_o => data_o,
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data_o_int => data_o_int,
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data_i_int => data_i_int,
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key_i_int => key_i_int,
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done_o_int => done_o_int,
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done_o => done_o
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);
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sbox1 : bram_block_a
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sbox1 : bram_block_a
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port map (
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port map (
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clk_a_i => clk_a_i,
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clk_a_i => clk_a_i,
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en_a_i => en_a_i,
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en_a_i => en_a_i,
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| Line 300... |
Line 339... |
--
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--
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key : key_scheduler
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key : key_scheduler
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port map (
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port map (
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clock => clock,
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clock => clock,
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load => load,
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load => load,
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key_i => key_i,
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key_i => key_i_int,
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key_o => key_o,
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key_o => key_o,
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done => done
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done => done
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);
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);
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--
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--
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count2bit : counter2bit
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count2bit : counter2bit
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Line 356... |
foldreg : folded_register
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foldreg : folded_register
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port map (
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port map (
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clk_i => clock,
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clk_i => clock,
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enc_i => enc,
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enc_i => enc,
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load_i => load,
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load_i => load,
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data_i => data_i,
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data_i => data_i_int,
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key_i => key_b,
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key_i => key_b,
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di_0_i => di_0_i,
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di_0_i => di_0_i,
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di_1_i => di_1_i,
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di_1_i => di_1_i,
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di_2_i => di_2_i,
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di_2_i => di_2_i,
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di_3_i => di_3_i,
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di_3_i => di_3_i,
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| Line 338... |
Line 377... |
elsif (clock = '1' and clock'event) then
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elsif (clock = '1' and clock'event) then
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fifo16x8 (127 downto 000) <= fifo16x8i (127 downto 000);
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fifo16x8 (127 downto 000) <= fifo16x8i (127 downto 000);
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if (done = '1') then
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if (done = '1') then
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load <= '1';
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load <= '1';
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else
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else
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load <= '0';
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-- load <= '0';
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load <= load_io;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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--
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--
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process(clear, clock)
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process(clear, clock)
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| Line 385... |
Line 425... |
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key_o_srl2 (43 downto 40) <= ( key_o_srl4_p (03), key_o_srl4_p (02), key_o_srl4_p (01), key_o_srl4_p (00) ) when ( enc = '0' ) else
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key_o_srl2 (43 downto 40) <= ( key_o_srl4_p (03), key_o_srl4_p (02), key_o_srl4_p (01), key_o_srl4_p (00) ) when ( enc = '0' ) else
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( key_o_srl2_p (03), key_o_srl2_p (02), key_o_srl2_p (01), key_o_srl2_p (00) );
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( key_o_srl2_p (03), key_o_srl2_p (02), key_o_srl2_p (01), key_o_srl2_p (00) );
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key_o_srl3 (43 downto 00) <= ( key_o_srl2 (43 downto 04) &
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key_o_srl3 (43 downto 00) <= ( key_o_srl2 (43 downto 04) &
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key_i (127 downto 096) &
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key_i_int (127 downto 096) &
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key_i (095 downto 064) &
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key_i_int (095 downto 064) &
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key_i (063 downto 032) &
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key_i_int (063 downto 032) &
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key_i (031 downto 000)
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key_i_int (031 downto 000)
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) when (done = '1') else
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) when (done = '1') else
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key_o_srl3 (43 downto 00);
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key_o_srl3 (43 downto 00);
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fifo16x8o (127 downto 000) <= fifo16x8i (127 downto 000) when (done = '1') else fifo16x8o (127 downto 000);
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fifo16x8o (127 downto 000) <= fifo16x8i (127 downto 000) when (done = '1') else fifo16x8o (127 downto 000);
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fifo16x8i (127 downto 000) <= ( fifo16x8 (095 downto 000) & output_o );
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fifo16x8i (127 downto 000) <= ( fifo16x8 (095 downto 000) & output_o );
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data_o (127 downto 000) <= fifo16x8o (127 downto 000);
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data_o_int (127 downto 000) <= fifo16x8o (127 downto 000);
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--
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--
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input (0) <= do_0_o;
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input (0) <= do_0_o;
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input (1) <= do_1_o;
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input (1) <= do_1_o;
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input (2) <= do_2_o;
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input (2) <= do_2_o;
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input (3) <= do_3_o;
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input (3) <= do_3_o;
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Line 463... |
di_0_i <= output (31 downto 24) when (enc = '0') else inv_mixcol_o (31 downto 24);
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di_0_i <= output (31 downto 24) when (enc = '0') else inv_mixcol_o (31 downto 24);
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di_1_i <= output (23 downto 16) when (enc = '0') else inv_mixcol_o (23 downto 16);
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di_1_i <= output (23 downto 16) when (enc = '0') else inv_mixcol_o (23 downto 16);
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di_2_i <= output (15 downto 08) when (enc = '0') else inv_mixcol_o (15 downto 08);
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di_2_i <= output (15 downto 08) when (enc = '0') else inv_mixcol_o (15 downto 08);
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di_3_i <= output (07 downto 00) when (enc = '0') else inv_mixcol_o (07 downto 00);
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di_3_i <= output (07 downto 00) when (enc = '0') else inv_mixcol_o (07 downto 00);
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--
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--
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key_b (127 downto 000) <= key_i (127 downto 000) when (enc = '0') else (key_o_srl3 (43) & key_o_srl3 (42) & key_o_srl3 (41) & key_o_srl3 (40));
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key_b (127 downto 000) <= key_i_int (127 downto 000) when (enc = '0') else (key_o_srl3 (43) & key_o_srl3 (42) & key_o_srl3 (41) & key_o_srl3 (40));
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current_key <= key_o_srl3(key_counter_down);
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current_key <= key_o_srl3(key_counter_down);
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process (clock, load)
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process (clock, load)
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begin
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begin
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