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[/] [minimips_superscalar/] [trunk/] [sources/] [minimips.vhd] - Diff between revs 2 and 18

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Rev 2 Rev 18
Line 50... Line 50...
    signal it_mat_clk : std_logic;          -- Synchronised hardware interruption
    signal it_mat_clk : std_logic;          -- Synchronised hardware interruption
    signal stop_pf : std_logic;             -- Lock the pc
    signal stop_pf : std_logic;             -- Lock the pc
    signal stop_pf2 : std_logic;            -- Lock the pc
    signal stop_pf2 : std_logic;            -- Lock the pc
    signal genop : std_logic;               -- envoi de nops
    signal genop : std_logic;               -- envoi de nops
    signal genop2 : std_logic;              -- envoi de nops
    signal genop2 : std_logic;              -- envoi de nops
    signal clock_out1, clock_out2 : std_logic; -- sem uso atual
 
    -- interface PF - EI
    -- interface PF - EI
    signal PF_pc : bus32;                   -- PC value
    signal PF_pc : bus32;                   -- PC value
    signal PF_pc_4 : bus32;
    signal PF_pc_4 : bus32;
 
 
    -- interface Controler - EI
    -- interface Controler - EI
Line 379... Line 378...
    );
    );
 
 
 
 
    U4_ex : pps_ex port map (
    U4_ex : pps_ex port map (
        clock => clock,
        clock => clock,
        clock2 => clock,
        clock2 => clock2,
        reset => reset,
        reset => reset,
        stop_all => stop_all,
        stop_all => stop_all,
        stop_all2 => stop_all2,               -- Unconditionnal locking of outputs
        stop_all2 => stop_all2,               -- Unconditionnal locking of outputs
        clear => interrupt,                 -- Clear the pipeline stage
        clear => interrupt,                 -- Clear the pipeline stage
 
 
Line 824... Line 823...
 
 
        -- Pipeline progress control signal
        -- Pipeline progress control signal
        stop_all       => stop_all2
        stop_all       => stop_all2
    );
    );
 
 
U14_clock_gate :  clock_gate port map (
U14_delay_gate : delay_gate port map (
        clock_in1   => clock,
 
        clock_in2   => clock2,
 
        clock_out1  => clock_out1,
 
        clock_out2  => clock_out2,
 
        gate1       => zero,
 
        gate2       => zero
 
    );
 
 
 
U15_delay_gate : delay_gate port map (
 
                clock => clock,
                clock => clock,
        in1   => DI_bra,
        in1   => DI_bra,
        in2   => bra_detect,
        in2   => bra_detect,
        in3   => EX_bra_confirm,
        in3   => EX_bra_confirm,
        in4   => alea,
        in4   => alea,

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