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This is a Mini-RISC CPU/Microcontroller that is mostly compatible with the
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PIC 16C57 from Microchip.
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Legal
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=====
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PIC, Microship, etc. are Trademarks of Microchip Technology Inc.
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I have no idea if implementing this core will or will not violate
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patents, copyrights or cause any other type of lawsuits.
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I provide this core AS IS, without any warrenties. If you decide to
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build this core, you are responsible for any legal resolutions, such
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as patents and copyrights, and perhaps others ....
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This source file(s) may be used and distributed without
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restriction provided that this copyright statement is not
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removed from the file and that any derivative work contains
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the original copyright notice and the associated disclaimer.
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THIS SOURCE FILE(S) IS/ARE PROVIDED "AS IS" AND WITHOUT ANY
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT
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LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND
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FITNESS FOR A PARTICULAR PURPOSE.
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Motivation
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==========
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After seeing the "free_risc8" on the free-ip web site, I got excited
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and downloaded the core. Pretty soon I found out that it had many
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many errors and omissions from the original 16C57. So I started looking
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at the code. This is when I realized it was very badly designed and
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could not be made run faster. So, I sat down and wrote my own PIC IP
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core last night. A lot of work was spend in writing test code to ensure
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that it was 100% compatible from the software point of view.
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- A PIC compatible Microcontroller that runs a lot faster
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- Separate (External to the core) Program Memory
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- Options to extend the core
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Compatibility
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=============
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This design should be fully software compatible to the Microchip Implementation
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of the PIC 16C57, except for the following extensions:
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- Port A is full 8 bits wide
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- Hardware stack is 4 level deep [original 2 levels] (can be easily expanded)
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- Executions of instructions that modify the PC has become a lot more expensive
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due to the pipeline and execution of instructions on every cycle.
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Any instruction that writes to the PC (PC as destination (f), call, goto, retlw)
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now takes 4 cycles to execute (instead of 2 in the origianl implementation).
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The 4 'skip' instructions, remain as in the original implmentation: 1 cycle
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if not skipped, 2 cycles if skipped.
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- Sampling of IO ports might be off
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- Timer and watchdog might be off a few cycles
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Performance
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===========
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- Single cycle instruction execution, except as noted above.
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- Here are results of some sample implementations:
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- Xilinx Spartan 2e ((Device: xc2s50e-6): Fmax: 80Mhz, Utilization: 30%
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- Xilinx Spartan2 (Device: xc2s30-6-cs144): Fmax: 50Mhz, Utilization: 66%, Ports: Tsu: 2.2nS, Tcq: 7.7nS
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- Xilinx Virtex (Device: xcv50-4-cs144) : Fmax: 40Mhz, Utilization: 35%, Ports: Tsu: 3.0nS, Tcq: 6.2nS
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- Xilinx VirtexE (Device: xcv50e-8-cs144): Fmax: 66Mhz, Utilization: 35%, Ports: Tsu: 1.7nS, Tcq: 4.5nS
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Half of the cycle time is spend in routing delays. My guess is that by placing
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proper locatiuon contrains and guiding the back-end tools, a significant
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speed improvement can be achieved ....
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- I estimat about 25K gates with the xilinx primitives, (excluding Register
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File and Programm Memory).
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Implementing the core
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=====================
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The only file you should edit if you really want to implement this core, is the
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'primitives.v' file. It contains all parts that can be optimized, depending on
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the technology used. It includes memories, and arithmetic modules.
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I added a primitives_xilinx,v file and xilinx_primitives.zip which contain
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primitives for xilinx.
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'risc_core.v' is the top level without program memory and tristate Io buffers for ports.
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This is probably a good starting point if you want to instantiate the core in to a larger
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design. If you just want a PIC clone, take a loot at 'risc_core_top.v', it was written
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with Xilinx FPGAs in mind, but should be easily addaptred to other vendors FPGAs - just
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replace the memory blocks ...
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To-Do
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=====
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Things that need to be done
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1) Write more test/compliance test vectors
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- Verify that all instructions after a goto/call/retlw/write to PCL are not executed
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- Verify ALU
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- Timer and Watchdog tests
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- Perhaps some other ereas ?
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2) Extensions ?
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- I guess this is on a "as needed" basis
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- A friend suggested to add registers that can be shared by two or more cores in a MP type configuration
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Author
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======
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I have been doing ASIC design, verification and synthesis for over 15 years.
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This core is only a "mid-night hack", and should used with caution.
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I'd also like to know if anyone will actually use this core. Please send me a
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note if you will !
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Rudolf Usselmann
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russelmann@hotmail.com
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Feel free to send me comments, suggestions and bug reports.
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