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[/] [minsoc/] [branches/] [rc-1.0/] [backend/] [spartan3a_dsp_kit/] [minsoc_bench_defines.v] - Diff between revs 69 and 70

Rev 69	Rev 70
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`timescale 1ns/100ps

`//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)`	`//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)`
`define GENERIC_FPGA	`define GENERIC_FPGA
`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting.	`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting.
`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down)	`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down)
`//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)`	`//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)`