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`define GENERIC_FPGA
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`define GENERIC_FPGA
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`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting.
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`define MEMORY_MODEL //simulation uses a memory model enabling INITIALIZE_MEMORY_MODEL. If you comment this, START_UP might be interesting.
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`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down)
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`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down)
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//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
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//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
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`define FREQ_NUM_FOR_NS 1000000000
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`define FREQ_NUM_FOR_NS 100000000
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`define FREQ 25000000
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`define FREQ 25000000
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`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ)
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`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ)
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`define ETH_PHY_FREQ 25000000
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`define ETH_PHY_FREQ 25000000
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`define INITIALIZE_MEMORY_MODEL //instantaneously initialize memory model with firmware
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`define INITIALIZE_MEMORY_MODEL //instantaneously initialize memory model with firmware
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//only use with the memory model.
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//only use with the memory model.
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//If you use the original memory (`define MEMORY_MODEL
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//If you use the original memory (`define MEMORY_MODEL
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//commented out), comment this too.
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//commented out), comment this too.
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`define TEST_UART
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//`define TEST_ETHERNET
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