URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [backend/] [std/] [minsoc_bench_defines.v] - Diff between revs 17 and 28

Rev 17	Rev 28
Line 1...	Line 1...

`timescale 1ns/100ps	`timescale 1ns/100ps

`//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)`	`//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)`
`define GENERIC_FPGA	`define GENERIC_FPGA
`define NO_CLOCK_DIVISION	`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down)
`define POSITIVE_RESET	`define POSITIVE_RESET
`//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)`	`//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)`

	`define FREQ_NUM_FOR_NS 1000000000

`define FREQ 25000000	`define FREQ 25000000
`define CLK_PERIOD (1000000000/`FREQ)	`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ)

`define ETH_PHY_FREQ 25000000	`define ETH_PHY_FREQ 25000000
`define ETH_PHY_PERIOD (1000000000/`ETH_PHY_FREQ) //40ns	`define ETH_PHY_PERIOD (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ) //40ns

`define UART_BAUDRATE 115200	`define UART_BAUDRATE 115200

`define VPI_DEBUG	`define VPI_DEBUG