URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [backend/] [std/] [minsoc_bench_defines.v] - Diff between revs 2 and 7

Rev 2	Rev 7
Line 2...	Line 2...
`timescale 1ns/100ps	`timescale 1ns/100ps

`//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)`	`//set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)`
`define GENERIC_FPGA	`define GENERIC_FPGA
`define NO_CLOCK_DIVISION	`define NO_CLOCK_DIVISION
	`define POSITIVE_RESET
`//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)`	`//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)`

`define FREQ 25000000	`define FREQ 25000000

`define CLK_PERIOD (1000000000/`FREQ)	`define CLK_PERIOD (1000000000/`FREQ)