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Rev 147 |
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`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down)
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`define NO_CLOCK_DIVISION //if commented out, generic clock division is implemented (odd divisors are rounded down)
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//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
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//~set RTL for simulation, override FPGA specific definitions (JTAG TAP, MEMORY and CLOCK DIVIDER)
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`define FREQ_NUM_FOR_NS 100000000
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`define FREQ_NUM_FOR_NS 100000000
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`define FREQ 25000000
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`define FREQ 10000000
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`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ)
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`define CLK_PERIOD (`FREQ_NUM_FOR_NS/`FREQ)
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`define ETH_PHY_FREQ 25000000
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`define ETH_PHY_FREQ 25000000
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`define ETH_PHY_PERIOD (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ) //40ns
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`define ETH_PHY_PERIOD (`FREQ_NUM_FOR_NS/`ETH_PHY_FREQ) //40ns
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`define UART_BAUDRATE 115200
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`define UART_BAUDRATE 9600
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`define VPI_DEBUG
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`define VPI_DEBUG
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//`define VCD_OUTPUT
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//`define WAVEFORM_OUTPUT
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//`define START_UP //pass firmware over spi to or1k_startup
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//`define START_UP //pass firmware over spi to or1k_startup
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`define INITIALIZE_MEMORY_MODEL //instantaneously initialize memory model with firmware
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`define INITIALIZE_MEMORY_MODEL //instantaneously initialize memory model with firmware
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//only use with the memory model.
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//only use with the memory model.
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