URL
https://opencores.org/ocsvn/minsoc/minsoc/trunk
[/] [minsoc/] [branches/] [rc-1.0/] [prj/] [src/] [minsoc_bench.prj] - Diff between revs 131 and 133
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 131 |
Rev 133 |
| Line 1... |
Line 1... |
PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog)
|
PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog)
|
PROJECT_SRC=(minsoc_bench_defines.v
|
PROJECT_SRC=(minsoc_bench_defines.v
|
minsoc_bench_clock.v
|
minsoc_bench.v
|
minsoc_bench_core.v
|
|
minsoc_memory_model.v
|
minsoc_memory_model.v
|
dbg_comm_vpi.v
|
dbg_comm_vpi.v
|
fpga_memory_primitives.v
|
fpga_memory_primitives.v
|
timescale.v)
|
timescale.v)
|
|
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.
