URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [prj/] [src/] [minsoc_top.prj] - Diff between revs 85 and 88

Rev 85	Rev 88
Line 1...	Line 1...
`PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog rtl/verilog/minsoc_startup)`	`PROJECT_DIR=(backend bench/verilog bench/verilog/vpi bench/verilog/sim_lib rtl/verilog rtl/verilog/minsoc_startup rtl/verilog/or1200/rtl/verilog rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog rtl/verilog/ethmac/rtl/verilog rtl/verilog/uart16550/rtl/verilog)`
`PROJECT_SRC=(minsoc_defines.v`	`PROJECT_SRC=(minsoc_defines.v`
`minsoc_bench_defines.v`
`minsoc_bench.v`
`minsoc_memory_model.v`
`dbg_comm_vpi.v`
`fpga_memory_primitives.v`
`timescale.v`	`timescale.v`
`minsoc_top.v`	`minsoc_top.v`
	`minsoc_tc_top.v`
	`minsoc_onchip_ram.v`
	`minsoc_onchip_ram_top.v`
	`minsoc_clock_manager.v`
	`altera_pll.v`
	`xilinx_dcm.v`
	`minsoc_xilinx_internal_jtag.v`
`spi_top.v`	`spi_top.v`
`spi_defines.v`	`spi_defines.v`
`spi_shift.v`	`spi_shift.v`
`spi_clgen.v`	`spi_clgen.v`
`OR1K_startup_generic.v`	`OR1K_startup_generic.v)`
`minsoc_tc_top.v`
`minsoc_onchip_ram.v`
`minsoc_clock_manager.v`
`minsoc_onchip_ram_top.v)`