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[/] [minsoc/] [branches/] [verilator/] [bench/] [verilog/] [minsoc_bench_clock.v] - Diff between revs 128 and 129

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Rev 128 Rev 129
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`include "minsoc_bench_defines.v"
`include "minsoc_bench_defines.v"
 
`include "minsoc_defines.v"
 
 
`include "timescale.v"
`include "timescale.v"
 
 
 
 
module minsoc_verilog_bench();
module minsoc_verilog_bench();
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    // Reset controller
    // Reset controller
    repeat (2) @ (negedge clock);
    repeat (2) @ (negedge clock);
    reset = RESET_LEVEL;
    reset = RESET_LEVEL;
    repeat (16) @ (negedge clock);
    repeat (16) @ (negedge clock);
    reset = ~RESET_LEVEL;
    reset = ~RESET_LEVEL;
 
 
end
end
 
 
//
//
//      Regular clocking and output
//      Regular clocking and output
//
//

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