OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [bench/] [verilog/] [minsoc_bench_clock.v] - Diff between revs 129 and 131

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 129 Rev 131
Line 2... Line 2...
`include "minsoc_defines.v"
`include "minsoc_defines.v"
 
 
`include "timescale.v"
`include "timescale.v"
 
 
 
 
module minsoc_verilog_bench();
module minsoc_bench_clock();
 
 
`ifdef POSITIVE_RESET
`ifdef POSITIVE_RESET
    localparam RESET_LEVEL = 1'b1;
    localparam RESET_LEVEL = 1'b1;
`elsif NEGATIVE_RESET
`elsif NEGATIVE_RESET
    localparam RESET_LEVEL = 1'b0;
    localparam RESET_LEVEL = 1'b0;
Line 14... Line 14...
    localparam RESET_LEVEL = 1'b1;
    localparam RESET_LEVEL = 1'b1;
`endif
`endif
 
 
reg clock, reset, eth_tx_clk, eth_rx_clk;
reg clock, reset, eth_tx_clk, eth_rx_clk;
 
 
minsoc_bench minsoc_bench_0(
minsoc_bench_core minsoc_bench_core_0(
    .clock(clock),
    .clock(clock),
    .reset(reset),
    .reset(reset),
    .eth_tx_clk(eth_tx_clk),
    .eth_tx_clk(eth_tx_clk),
    .eth_rx_clk(eth_rx_clk)
    .eth_rx_clk(eth_rx_clk)
);
);

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.