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[/] [minsoc/] [branches/] [verilator/] [bench/] [verilog/] [minsoc_bench_core.v] - Diff between revs 127 and 128

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Rev 127 Rev 128
Line 2... Line 2... 
`include "minsoc_defines.v"
 
`include "minsoc_defines.v"
 
`include "or1200_defines.v"
 
`include "or1200_defines.v"
 
 
 
 
 
`include "timescale.v"
 
`include "timescale.v"
 
 
 
 
 
module minsoc_bench();
 
module minsoc_bench(
 
 
 
    clock,
 
`ifdef POSITIVE_RESET
 
    reset,
 
    localparam RESET_LEVEL = 1'b1;
 
    eth_tx_clk,
 
`elsif NEGATIVE_RESET
 
    eth_rx_clk
 
    localparam RESET_LEVEL = 1'b0;
 
);
 
`else
 
 
 
    localparam RESET_LEVEL = 1'b1;
 
 
 
`endif
 
 
 
 
 
 
 
reg clock, reset;
 
input clock, reset, eth_tx_clk, eth_rx_clk;
 
 
 
 
 
//Debug interface
 
//Debug interface
 
wire dbg_tms_i;
 
wire dbg_tms_i;
 
wire dbg_tck_i;
 
wire dbg_tck_i;
 
wire dbg_tdi_i;
 
wire dbg_tdi_i;
Line 36... Line 33... 
 
 
 
 
//ETH wires
 
//ETH wires
 
reg eth_col;
 
reg eth_col;
 
reg eth_crs;
 
reg eth_crs;
 
wire eth_trst;
 
wire eth_trst;
 
reg eth_tx_clk;
 
 
 
wire eth_tx_en;
 
wire eth_tx_en;
 
wire eth_tx_er;
 
wire eth_tx_er;
 
wire [3:0] eth_txd;
 
wire [3:0] eth_txd;
 
reg eth_rx_clk;
 
 
 
reg eth_rx_dv;
 
reg eth_rx_dv;
 
reg eth_rx_er;
 
reg eth_rx_er;
 
reg [3:0] eth_rxd;
 
reg [3:0] eth_rxd;
 
reg eth_fds_mdint;
 
reg eth_fds_mdint;
 
wire eth_mdc;
 
wire eth_mdc;
Line 76... Line 71... 
integer initialize, firmware_size, ptr;
 
integer initialize, firmware_size, ptr;
 
reg [8*64:0] file_name;
 
reg [8*64:0] file_name;
 
reg load_file;
 
reg load_file;
 
 
 
 
 
initial begin
 
initial begin
 
    reset = ~RESET_LEVEL;
 
 
 
    clock = 1'b0;
 
 
 
    design_ready = 1'b0;
 
    design_ready = 1'b0;
 
    uart_echo = 1'b1;
 
    uart_echo = 1'b1;
 
 
 
 
 
`ifndef NO_CLOCK_DIVISION
 
`ifndef NO_CLOCK_DIVISION
 
    minsoc_top_0.clk_adjust.clk_int = 1'b0;
 
    minsoc_top_0.clk_adjust.clk_int = 1'b0;
Line 92... Line 85... 
 
 
 
 
        eth_col = 1'b0;
 
        eth_col = 1'b0;
 
        eth_crs = 1'b0;
 
        eth_crs = 1'b0;
 
        eth_fds_mdint = 1'b1;
 
        eth_fds_mdint = 1'b1;
 
        eth_rx_er = 1'b0;
 
        eth_rx_er = 1'b0;
 
 
 
 
 
        eth_tx_clk = 1'b0;
 
 
 
        eth_rx_clk = 1'b0;
 
 
 
        eth_rxd = 4'h0;
 
        eth_rxd = 4'h0;
 
        eth_rx_dv = 1'b0;
 
        eth_rx_dv = 1'b0;
 
 
 
 
 
 
 
 
 
//dual and two port rams from FPGA memory instances have to be initialized to 0
 
//dual and two port rams from FPGA memory instances have to be initialized to 0
Line 136... Line 126... 
        $display("Memory model initialized with firmware:");
 
        $display("Memory model initialized with firmware:");
 
        $display("%s", file_name);
 
        $display("%s", file_name);
 
        $display("%d Bytes loaded from %d ...", initialize , firmware_size);
 
        $display("%d Bytes loaded from %d ...", initialize , firmware_size);
 
`endif
 
`endif
 
 
 
 
 
    // Reset controller
 
 
 
    repeat (2) @ (negedge clock);
 
 
 
    reset = RESET_LEVEL;
 
 
 
    repeat (16) @ (negedge clock);
 
 
 
    reset = ~RESET_LEVEL;
 
 
 
 
 
 
 
`ifdef START_UP
 
`ifdef START_UP
 
        // Pass firmware over spi to or1k_startup
 
        // Pass firmware over spi to or1k_startup
 
        ptr = 0;
 
        ptr = 0;
 
        //read dummy
 
        //read dummy
 
        send_spi(program_mem[ptr]);
 
        send_spi(program_mem[ptr]);
Line 290... Line 274... 
            else
 
            else
 
                $display("UART interrupt failed.");
 
                $display("UART interrupt failed.");
 
            uart_echo = 1'b1;
 
            uart_echo = 1'b1;
 
 
 
 
 
            if ( hello == "Hello World." )
 
            if ( hello == "Hello World." )
 
                $display("UART firmware test completed, behaving correclty.");
 
                $display("UART firmware test completed, behaving correctly.");
 
            else
 
            else
 
                $display("UART firmware test completed, failed.");
 
                $display("UART firmware test completed, failed.");
 
    end
 
    end
 
endtask
 
endtask
 
 
 
 
Line 313... Line 297... 
            $display("Ethernet test completed.");
 
            $display("Ethernet test completed.");
 
    end
 
    end
 
endtask
 
endtask
 
 
 
 
 
 
 
 
 
//
 
 
 
//      Regular clocking and output
 
 
 
//
 
 
 
always begin
 
 
 
    #((`CLK_PERIOD)/2) clock <= ~clock;
 
 
 
end
 
 
 
 
 
 
 
`ifdef VCD_OUTPUT
 
`ifdef VCD_OUTPUT
 
initial begin
 
initial begin
 
        $dumpfile("../results/minsoc_wave.vcd");
 
        $dumpfile("../results/minsoc_wave.vcd");
 
        $dumpvars();
 
        $dumpvars();
 
end
 
end
Line 594... Line 571... 
        crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]};
 
        crc32_result = ~{temp[7:0], temp[15:8], temp[23:16], temp[31:24]};
 
    end
 
    end
 
endtask
 
endtask
 
//~CRC32
 
//~CRC32
 
 
 
 
 
//Generate tx and rx clocks
 
 
 
always begin
 
 
 
        #((`ETH_PHY_PERIOD)/2) eth_tx_clk <= ~eth_tx_clk;
 
 
 
end
 
 
 
always begin
 
 
 
        #((`ETH_PHY_PERIOD)/2) eth_rx_clk <= ~eth_rx_clk;
 
 
 
end
 
 
 
//~Generate tx and rx clocks
 
 
 
 
 
 
 
`endif // !ETHERNET
 
`endif // !ETHERNET
 
//~MAC_DATA
 
//~MAC_DATA
 
 
 
 
 
 
 
 
 
 
 
 
Line 916... Line 884... 
`endif
 
`endif
 
`endif
 
`endif
 
    end
 
    end
 
endtask
 
endtask
 
 
 
 
 
 
 
 
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 
 
 
 
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