URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [bench/] [verilog/] [minsoc_bench_core.v] - Diff between revs 17 and 28

Rev 17	Rev 28
Line 61...	Line 61...

`initial begin`	`initial begin`
`reset = 1'b0;`	`reset = 1'b0;`
`clock = 1'b0;`	`clock = 1'b0;`

	`ifndef NO_CLOCK_DIVISION
	`minsoc_top_0.clk_adjust.clk_int = 1'b0;`
	`minsoc_top_0.clk_adjust.clock_divisor = 32'h0000_0000;`
	`endif

`uart_srx = 1'b1;`	`uart_srx = 1'b1;`

`eth_col = 1'b0;`	`eth_col = 1'b0;`
`eth_crs = 1'b0;`	`eth_crs = 1'b0;`
`eth_fds_mdint = 1'b1;`	`eth_fds_mdint = 1'b1;`
Line 272...	Line 277...
`endif	`endif
`//~SPI START_UP`	`//~SPI START_UP`

`//UART`	`//UART`
`ifdef UART	`ifdef UART
localparam UART_TX_WAIT = (`FREQ / `UART_BAUDRATE) * `CLK_PERIOD;	localparam UART_TX_WAIT = (`FREQ_NUM_FOR_NS / `UART_BAUDRATE);

`task uart_send;`	`task uart_send;`
`input [7:0] data;`	`input [7:0] data;`
`integer i;`	`integer i;`
`begin`	`begin`