URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [bench/] [verilog/] [minsoc_bench_core.v] - Diff between revs 28 and 59

Rev 28	Rev 59
Line 58...	Line 58...
`integer initialize, final, ptr;`	`integer initialize, final, ptr;`
`reg [8*64:0] file_name;`	`reg [8*64:0] file_name;`
`reg load_file;`	`reg load_file;`

`initial begin`	`initial begin`
`reset = 1'b0;`	reset = ~`RESET_LEVEL;
`clock = 1'b0;`	`clock = 1'b0;`

`ifndef NO_CLOCK_DIVISION	`ifndef NO_CLOCK_DIVISION
`minsoc_top_0.clk_adjust.clk_int = 1'b0;`	`minsoc_top_0.clk_adjust.clk_int = 1'b0;`
`minsoc_top_0.clk_adjust.clock_divisor = 32'h0000_0000;`	`minsoc_top_0.clk_adjust.clock_divisor = 32'h0000_0000;`
Line 118...	Line 118...
`$display("%d Bytes loaded from %d ...", initialize , final);`	`$display("%d Bytes loaded from %d ...", initialize , final);`
`endif	`endif

`// Reset controller`	`// Reset controller`
`repeat (2) @ (negedge clock);`	`repeat (2) @ (negedge clock);`
`reset = 1'b1;`	reset = `RESET_LEVEL;
`repeat (16) @ (negedge clock);`	`repeat (16) @ (negedge clock);`
`reset = 1'b0;`	reset = ~`RESET_LEVEL;

`ifdef START_UP	`ifdef START_UP
`// Pass firmware over spi to or1k_startup`	`// Pass firmware over spi to or1k_startup`
`ptr = 0;`	`ptr = 0;`
`//read dummy`	`//read dummy`