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https://opencores.org/ocsvn/minsoc/minsoc/trunk
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Rev 59 |
Line 58... |
Line 58... |
integer initialize, final, ptr;
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integer initialize, final, ptr;
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reg [8*64:0] file_name;
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reg [8*64:0] file_name;
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reg load_file;
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reg load_file;
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initial begin
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initial begin
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reset = 1'b0;
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reset = ~`RESET_LEVEL;
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clock = 1'b0;
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clock = 1'b0;
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`ifndef NO_CLOCK_DIVISION
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`ifndef NO_CLOCK_DIVISION
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minsoc_top_0.clk_adjust.clk_int = 1'b0;
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minsoc_top_0.clk_adjust.clk_int = 1'b0;
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minsoc_top_0.clk_adjust.clock_divisor = 32'h0000_0000;
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minsoc_top_0.clk_adjust.clock_divisor = 32'h0000_0000;
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Line 118... |
Line 118... |
$display("%d Bytes loaded from %d ...", initialize , final);
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$display("%d Bytes loaded from %d ...", initialize , final);
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`endif
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`endif
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// Reset controller
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// Reset controller
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repeat (2) @ (negedge clock);
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repeat (2) @ (negedge clock);
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reset = 1'b1;
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reset = `RESET_LEVEL;
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repeat (16) @ (negedge clock);
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repeat (16) @ (negedge clock);
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reset = 1'b0;
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reset = ~`RESET_LEVEL;
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`ifdef START_UP
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`ifdef START_UP
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// Pass firmware over spi to or1k_startup
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// Pass firmware over spi to or1k_startup
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ptr = 0;
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ptr = 0;
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//read dummy
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//read dummy
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