URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [tags/] [release-0.9/] [bench/] [verilog/] [minsoc_bench.v] - Diff between revs 10 and 11

Rev 10	Rev 11
Line 52...	Line 52...
`reg load_file;`	`reg load_file;`

`initial begin`	`initial begin`
`reset = 1'b0;`	`reset = 1'b0;`
`clock = 1'b0;`	`clock = 1'b0;`
	`uart_srx = 1'b1;`

`//dual and two port rams from FPGA memory instances have to be initialized to`	`//dual and two port rams from FPGA memory instances have to be initialized to`
`//0`	`//0`
`init_fpga_memory();`	`init_fpga_memory();`