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[/] [minsoc/] [tags/] [release-0.9/] [bench/] [verilog/] [minsoc_bench.v] - Diff between revs 2 and 4

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//
//
// Testbench mechanics
// Testbench mechanics
//
//
reg [7:0] program_mem[(1<<((`MEMORY_ADR_WIDTH)+11+2))-1:0];
reg [7:0] program_mem[(1<<(`MEMORY_ADR_WIDTH+2))-1:0];
integer initialize, final, ptr;
integer initialize, final, ptr;
reg [8*64:0] file_name;
reg [8*64:0] file_name;
reg load_file;
reg load_file;
initial begin
initial begin
        load_file = 1'b0;
        load_file = 1'b0;

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