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https://opencores.org/ocsvn/minsoc/minsoc/trunk
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| Rev 4 |
Rev 8 |
| Line 47... |
Line 47... |
//
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//
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reg [7:0] program_mem[(1<<(`MEMORY_ADR_WIDTH+2))-1:0];
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reg [7:0] program_mem[(1<<(`MEMORY_ADR_WIDTH+2))-1:0];
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integer initialize, final, ptr;
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integer initialize, final, ptr;
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reg [8*64:0] file_name;
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reg [8*64:0] file_name;
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reg load_file;
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reg load_file;
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initial begin
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initial begin
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reset = 1'b0;
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clock = 1'b0;
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load_file = 1'b0;
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load_file = 1'b0;
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`ifdef INITIALIZE_MEMORY_MODEL
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`ifdef INITIALIZE_MEMORY_MODEL
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load_file = 1'b1;
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load_file = 1'b1;
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`endif
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`endif
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`ifdef START_UP
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`ifdef START_UP
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load_file = 1'b1;
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load_file = 1'b1;
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`endif
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`endif
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//get firmware hex file from command line input
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//get firmware hex file from command line input
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if ( load_file ) begin
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if ( load_file ) begin
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if ( ! $value$plusargs("file_name=%s", file_name) || file_name == 0 ) begin
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if ( ! $value$plusargs("file_name=%s", file_name) || file_name == 0 ) begin
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$display("ERROR: please specify an input file to start.");
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$display("ERROR: please specify an input file to start.");
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$finish;
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$finish;
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Line 214... |
);
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);
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`endif // !ETHERNET
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`endif // !ETHERNET
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//
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//
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// Regular clocking, reset and output
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// Regular clocking and output
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//
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//
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initial begin
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clock <= 1'b0;
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reset <= 1'b0;
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end
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always begin
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always begin
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#((`CLK_PERIOD)/2) clock <= ~clock;
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#((`CLK_PERIOD)/2) clock <= ~clock;
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end
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end
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`ifdef VCD_OUTPUT
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`ifdef VCD_OUTPUT
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initial begin
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initial begin
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$dumpfile("../results/minsoc_wave.vcd");
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$dumpfile("../results/minsoc_wave.vcd");
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$dumpvars();
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$dumpvars();
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end
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end
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