| Line 297... |
Line 297... |
// By default implementation of l.addc/l.addic
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// By default implementation of l.addc/l.addic
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// instructions is enabled in case you need them.
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// instructions is enabled in case you need them.
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// If you don't use them, then disable implementation
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// If you don't use them, then disable implementation
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// to save area.
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// to save area.
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//
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//
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//`define OR1200_IMPL_ADDC
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`define OR1200_IMPL_ADDC
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//
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//
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// Implement l.sub instruction
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// Implement l.sub instruction
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//
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//
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// By default implementation of l.sub instructions
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// By default implementation of l.sub instructions
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| Line 319... |
Line 319... |
// to be compliant with the simulator. However SR[CY]
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// to be compliant with the simulator. However SR[CY]
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// is explicitly only used by l.addc/l.addic/l.sub
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// is explicitly only used by l.addc/l.addic/l.sub
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// instructions and if these three insns are not
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// instructions and if these three insns are not
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// implemented there is not much point having SR[CY].
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// implemented there is not much point having SR[CY].
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//
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//
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//`define OR1200_IMPL_CY
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`define OR1200_IMPL_CY
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//
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// Implement carry bit SR[OV]
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//
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// Compiler doesn't use this, but other code may like
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// to.
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//
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`define OR1200_IMPL_OV
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//
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// Implement carry bit SR[OVE]
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//
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// Overflow interrupt indicator. When enabled, SR[OV] flag
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// does not remain asserted after exception.
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//
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`define OR1200_IMPL_OVE
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//
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//
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// Implement rotate in the ALU
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// Implement rotate in the ALU
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//
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//
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// At the time of writing this, or32
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// At the time of writing this, or32
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| Line 340... |
Line 357... |
//`define OR1200_IMPL_ALU_ROTATE
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//`define OR1200_IMPL_ALU_ROTATE
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//
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//
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// Type of ALU compare to implement
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// Type of ALU compare to implement
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//
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//
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// Try either one to find what yields
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// Try to find which synthesizes with
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// higher clock frequencyin your case.
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// most efficient logic use or highest speed.
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//
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//
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//`define OR1200_IMPL_ALU_COMP1
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//`define OR1200_IMPL_ALU_COMP1
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`define OR1200_IMPL_ALU_COMP2
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//`define OR1200_IMPL_ALU_COMP2
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`define OR1200_IMPL_ALU_COMP3
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//
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//
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// Implement Find First/Last '1'
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// Implement Find First/Last '1'
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//
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//
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`define OR1200_IMPL_ALU_FFL1
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`define OR1200_IMPL_ALU_FFL1
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//
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//
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// Implement l.cust5 ALU instruction
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//
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//`define OR1200_IMPL_ALU_CUST5
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//
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// Implement l.extXs and l.extXz instructions
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//
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`define OR1200_IMPL_ALU_EXT
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//
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// Implement multiplier
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// Implement multiplier
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//
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//
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// By default multiplier is implemented
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// By default multiplier is implemented
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//
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//
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`define OR1200_MULT_IMPLEMENTED
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`define OR1200_MULT_IMPLEMENTED
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| Line 393... |
Line 421... |
//
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//
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// Implement HW Single Precision FPU
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// Implement HW Single Precision FPU
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//
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//
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//`define OR1200_FPU_IMPLEMENTED
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//`define OR1200_FPU_IMPLEMENTED
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//
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//
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// Clock ratio RISC clock versus WB clock
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// Clock ratio RISC clock versus WB clock
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//
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//
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// If you plan to run WB:RISC clock fixed to 1:1, disable
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// If you plan to run WB:RISC clock fixed to 1:1, disable
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// both defines
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// both defines
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| Line 450... |
Line 477... |
`endif
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`endif
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//
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//
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// ALUOPs
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// ALUOPs
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//
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//
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`define OR1200_ALUOP_WIDTH 4
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`define OR1200_ALUOP_WIDTH 5
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`define OR1200_ALUOP_NOP 4'd4
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`define OR1200_ALUOP_NOP 5'b0_0100
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/* Order defined by arith insns that have two source operands both in regs
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/* LS-nibble encodings correspond to bits [3:0] of instruction */
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(see binutils/include/opcode/or32.h) */
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`define OR1200_ALUOP_ADD 5'b0_0000 // 0
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`define OR1200_ALUOP_ADD 4'd0
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`define OR1200_ALUOP_ADDC 5'b0_0001 // 1
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`define OR1200_ALUOP_ADDC 4'd1
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`define OR1200_ALUOP_SUB 5'b0_0010 // 2
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`define OR1200_ALUOP_SUB 4'd2
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`define OR1200_ALUOP_AND 5'b0_0011 // 3
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`define OR1200_ALUOP_AND 4'd3
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`define OR1200_ALUOP_OR 5'b0_0100 // 4
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`define OR1200_ALUOP_OR 4'd4
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`define OR1200_ALUOP_XOR 5'b0_0101 // 5
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`define OR1200_ALUOP_XOR 4'd5
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`define OR1200_ALUOP_MUL 5'b0_0110 // 6
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`define OR1200_ALUOP_MUL 4'd6
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`define OR1200_ALUOP_RESERVED 5'b0_0111 // 7
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`define OR1200_ALUOP_CUST5 4'd7
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`define OR1200_ALUOP_SHROT 5'b0_1000 // 8
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`define OR1200_ALUOP_SHROT 4'd8
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`define OR1200_ALUOP_DIV 5'b0_1001 // 9
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`define OR1200_ALUOP_DIV 4'd9
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`define OR1200_ALUOP_DIVU 5'b0_1010 // a
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`define OR1200_ALUOP_DIVU 4'd10
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`define OR1200_ALUOP_MULU 5'b0_1011 // b
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`define OR1200_ALUOP_MULU 4'd11
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`define OR1200_ALUOP_EXTHB 5'b0_1100 // c
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/* Values sent to ALU from decode unit - not strictly defined by ISA */
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`define OR1200_ALUOP_EXTW 5'b0_1101 // d
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`define OR1200_ALUOP_MOVHI 4'd12
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`define OR1200_ALUOP_CMOV 5'b0_1110 // e
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`define OR1200_ALUOP_COMP 4'd13
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`define OR1200_ALUOP_FFL1 5'b0_1111 // f
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`define OR1200_ALUOP_MTSR 4'd14
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`define OR1200_ALUOP_MFSR 4'd15
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/* Values sent to ALU from decode unit - not defined by ISA */
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`define OR1200_ALUOP_CMOV 4'd14
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`define OR1200_ALUOP_COMP 5'b1_0000 // Comparison
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`define OR1200_ALUOP_FFL1 4'd15
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`define OR1200_ALUOP_MOVHI 5'b1_0001 // Move-high
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`define OR1200_ALUOP_CUST5 5'b1_0010 // l.cust5
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// ALU instructions second opcode field (previously multicycle field in
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// ALU instructions second opcode field
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// machine word)
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`define OR1200_ALUOP2_POS 9:6
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`define OR1200_ALUOP2_POS 9:8
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`define OR1200_ALUOP2_WIDTH 4
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`define OR1200_ALUOP2_WIDTH 2
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//
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//
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// MACOPs
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// MACOPs
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//
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//
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`define OR1200_MACOP_WIDTH 3
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`define OR1200_MACOP_WIDTH 3
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| Line 492... |
Line 517... |
`define OR1200_MACOP_MSB 3'b010
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`define OR1200_MACOP_MSB 3'b010
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//
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//
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// Shift/rotate ops
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// Shift/rotate ops
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//
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//
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`define OR1200_SHROTOP_WIDTH 2
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`define OR1200_SHROTOP_WIDTH 4
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`define OR1200_SHROTOP_NOP 2'd0
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`define OR1200_SHROTOP_NOP 4'd0
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`define OR1200_SHROTOP_SLL 2'd0
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`define OR1200_SHROTOP_SLL 4'd0
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`define OR1200_SHROTOP_SRL 2'd1
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`define OR1200_SHROTOP_SRL 4'd1
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`define OR1200_SHROTOP_SRA 2'd2
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`define OR1200_SHROTOP_SRA 4'd2
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`define OR1200_SHROTOP_ROR 2'd3
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`define OR1200_SHROTOP_ROR 4'd3
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//
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// Zero/Sign Extend ops
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//
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`define OR1200_EXTHBOP_WIDTH 4
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`define OR1200_EXTHBOP_BS 4'h1
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`define OR1200_EXTHBOP_HS 4'h0
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`define OR1200_EXTHBOP_BZ 4'h3
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`define OR1200_EXTHBOP_HZ 4'h2
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`define OR1200_EXTWOP_WIDTH 4
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`define OR1200_EXTWOP_WS 4'h0
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`define OR1200_EXTWOP_WZ 4'h1
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// Execution cycles per instruction
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// Execution cycles per instruction
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`define OR1200_MULTICYCLE_WIDTH 3
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`define OR1200_MULTICYCLE_WIDTH 3
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`define OR1200_ONE_CYCLE 3'd0
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`define OR1200_ONE_CYCLE 3'd0
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`define OR1200_TWO_CYCLES 3'd1
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`define OR1200_TWO_CYCLES 3'd1
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// Execution control which will "wait on" a module to finish
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// Execution control which will "wait on" a module to finish
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`define OR1200_WAIT_ON_WIDTH 2
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`define OR1200_WAIT_ON_WIDTH 2
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`define OR1200_WAIT_ON_FPU `OR1200_WAIT_ON_WIDTH'd1
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`define OR1200_WAIT_ON_NOTHING `OR1200_WAIT_ON_WIDTH'd0
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`define OR1200_WAIT_ON_MTSPR `OR1200_WAIT_ON_WIDTH'd2
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`define OR1200_WAIT_ON_MULTMAC `OR1200_WAIT_ON_WIDTH'd1
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`define OR1200_WAIT_ON_FPU `OR1200_WAIT_ON_WIDTH'd2
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`define OR1200_WAIT_ON_MTSPR `OR1200_WAIT_ON_WIDTH'd3
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// Operand MUX selects
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// Operand MUX selects
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`define OR1200_SEL_WIDTH 2
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`define OR1200_SEL_WIDTH 2
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`define OR1200_SEL_RF 2'd0
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`define OR1200_SEL_RF 2'd0
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`define OR1200_SEL_IMM 2'd1
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`define OR1200_SEL_IMM 2'd1
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| Line 648... |
Line 688... |
`define OR1200_OR32_JAL 6'b000001
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`define OR1200_OR32_JAL 6'b000001
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`define OR1200_OR32_BNF 6'b000011
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`define OR1200_OR32_BNF 6'b000011
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`define OR1200_OR32_BF 6'b000100
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`define OR1200_OR32_BF 6'b000100
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`define OR1200_OR32_NOP 6'b000101
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`define OR1200_OR32_NOP 6'b000101
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`define OR1200_OR32_MOVHI 6'b000110
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`define OR1200_OR32_MOVHI 6'b000110
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`define OR1200_OR32_MACRC 6'b000110
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`define OR1200_OR32_XSYNC 6'b001000
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`define OR1200_OR32_XSYNC 6'b001000
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`define OR1200_OR32_RFE 6'b001001
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`define OR1200_OR32_RFE 6'b001001
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/* */
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/* */
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`define OR1200_OR32_JR 6'b010001
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`define OR1200_OR32_JR 6'b010001
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`define OR1200_OR32_JALR 6'b010010
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`define OR1200_OR32_JALR 6'b010010
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| Line 679... |
Line 720... |
`define OR1200_OR32_SW 6'b110101
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`define OR1200_OR32_SW 6'b110101
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`define OR1200_OR32_SB 6'b110110
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`define OR1200_OR32_SB 6'b110110
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`define OR1200_OR32_SH 6'b110111
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`define OR1200_OR32_SH 6'b110111
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`define OR1200_OR32_ALU 6'b111000
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`define OR1200_OR32_ALU 6'b111000
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`define OR1200_OR32_SFXX 6'b111001
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`define OR1200_OR32_SFXX 6'b111001
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//`define OR1200_OR32_CUST5 6'b111100
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`define OR1200_OR32_CUST5 6'b111100
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/////////////////////////////////////////////////////
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/////////////////////////////////////////////////////
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//
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//
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// Exceptions
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// Exceptions
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//
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//
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| Line 801... |
Line 841... |
`define OR1200_SR_DME 5
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`define OR1200_SR_DME 5
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`define OR1200_SR_IME 6
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`define OR1200_SR_IME 6
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`define OR1200_SR_LEE 7
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`define OR1200_SR_LEE 7
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`define OR1200_SR_CE 8
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`define OR1200_SR_CE 8
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`define OR1200_SR_F 9
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`define OR1200_SR_F 9
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`define OR1200_SR_CY 10 // Unused
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`define OR1200_SR_CY 10 // Optional
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`define OR1200_SR_OV 11 // Unused
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`define OR1200_SR_OV 11 // Optional
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`define OR1200_SR_OVE 12 // Unused
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`define OR1200_SR_OVE 12 // Optional
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`define OR1200_SR_DSX 13 // Unused
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`define OR1200_SR_DSX 13 // Unused
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`define OR1200_SR_EPH 14
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`define OR1200_SR_EPH 14
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`define OR1200_SR_FO 15
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`define OR1200_SR_FO 15
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`define OR1200_SR_TED 16
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`define OR1200_SR_TED 16
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`define OR1200_SR_CID 31:28 // Unimplemented
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`define OR1200_SR_CID 31:28 // Unimplemented
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| Line 1617... |
Line 1657... |
`define OR1200_DMMUCFGR_NTW 2'h0 // 1 TLB way
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`define OR1200_DMMUCFGR_NTW 2'h0 // 1 TLB way
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`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW // Num TLB sets
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`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW // Num TLB sets
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`define OR1200_DMMUCFGR_NAE 3'h0 // No ATB entries
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`define OR1200_DMMUCFGR_NAE 3'h0 // No ATB entries
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`define OR1200_DMMUCFGR_CRI 1'b0 // No control register
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`define OR1200_DMMUCFGR_CRI 1'b0 // No control register
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`define OR1200_DMMUCFGR_PRI 1'b0 // No protection reg
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`define OR1200_DMMUCFGR_PRI 1'b0 // No protection reg
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`define OR1200_DMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl.
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`define OR1200_DMMUCFGR_TEIRI 1'b0 // TLB entry inv reg NOT impl.
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`define OR1200_DMMUCFGR_HTR 1'b0 // No HW TLB reload
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`define OR1200_DMMUCFGR_HTR 1'b0 // No HW TLB reload
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`define OR1200_DMMUCFGR_RES1 20'h00000
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`define OR1200_DMMUCFGR_RES1 20'h00000
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`endif
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`endif
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// IMMUCFGR fields
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// IMMUCFGR fields
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| Line 1648... |
Line 1688... |
`define OR1200_IMMUCFGR_NTW 2'h0 // 1 TLB way
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`define OR1200_IMMUCFGR_NTW 2'h0 // 1 TLB way
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`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW // Num TLB sets
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`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW // Num TLB sets
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`define OR1200_IMMUCFGR_NAE 3'h0 // No ATB entry
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`define OR1200_IMMUCFGR_NAE 3'h0 // No ATB entry
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`define OR1200_IMMUCFGR_CRI 1'b0 // No control reg
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`define OR1200_IMMUCFGR_CRI 1'b0 // No control reg
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`define OR1200_IMMUCFGR_PRI 1'b0 // No protection reg
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`define OR1200_IMMUCFGR_PRI 1'b0 // No protection reg
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`define OR1200_IMMUCFGR_TEIRI 1'b1 // TLB entry inv reg impl
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`define OR1200_IMMUCFGR_TEIRI 1'b0 // TLB entry inv reg NOT impl
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`define OR1200_IMMUCFGR_HTR 1'b0 // No HW TLB reload
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`define OR1200_IMMUCFGR_HTR 1'b0 // No HW TLB reload
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`define OR1200_IMMUCFGR_RES1 20'h00000
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`define OR1200_IMMUCFGR_RES1 20'h00000
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`endif
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`endif
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// DCCFGR fields
|
// DCCFGR fields
|
