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[/] [minsoc/] [trunk/] [bench/] [verilog/] [minsoc_memory_model.v] - Diff between revs 60 and 71

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//
//
// Revision 1.0 2009/08/18 15:15:00   fajardo
// Revision 1.0 2009/08/18 15:15:00   fajardo
// Created interface and tested
// Created interface and tested
//
//
 
 
 
`include "timescale.v"
 
 
module minsoc_memory_model (
module minsoc_memory_model (
  wb_clk_i, wb_rst_i,
  wb_clk_i, wb_rst_i,
 
 
  wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
  wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,

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