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[/] [minsoc/] [trunk/] [bench/] [verilog/] [minsoc_memory_model.v] - Diff between revs 2 and 60
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// Revision 1.0 2009/08/18 15:15:00 fajardo
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// Revision 1.0 2009/08/18 15:15:00 fajardo
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// Created interface and tested
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// Created interface and tested
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//
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//
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module minsoc_onchip_ram_top (
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module minsoc_memory_model (
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wb_clk_i, wb_rst_i,
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wb_clk_i, wb_rst_i,
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wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
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wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
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wb_stb_i, wb_ack_o, wb_err_o
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wb_stb_i, wb_ack_o, wb_err_o
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);
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);
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