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[/] [minsoc/] [trunk/] [bench/] [verilog/] [sim_lib/] [fpga_memory_primitives.v] - Diff between revs 17 and 27

Rev 17	Rev 27
Line 11...	Line 11...
`q`	`q`
`);`	`);`

`parameter lpm_width = 8;`	`parameter lpm_width = 8;`
`parameter lpm_widthad = 11;`	`parameter lpm_widthad = 11;`
	`parameter lpm_indata = "REGISTERED"; //This 4 parameters are included only to avoid warnings`
	`parameter lpm_address_control = "REGISTERED"; //they are not accessed inside the module. OR1200 uses this`
	`parameter lpm_outdata = "UNREGISTERED"; //configuration set on all its instantiations, so this is fine.`
	`parameter lpm_hint = "USE_EAB=ON"; //It may not be fine, if you are adding this library to your`
	`//own system, which uses this module with another configuration.`
`localparam dw = lpm_width;`	`localparam dw = lpm_width;`
`localparam aw = lpm_widthad;`	`localparam aw = lpm_widthad;`

`input [aw-1:0] address;`	`input [aw-1:0] address;`
`input inclock;`	`input inclock;`
Line 28...	Line 32...
`reg [aw-1:0] addr_reg; // RAM address register`	`reg [aw-1:0] addr_reg; // RAM address register`

`//`	`//`
`// Data output drivers`	`// Data output drivers`
`//`	`//`
`assign doq = mem[addr_reg];`	`assign q = mem[addr_reg];`

`//`	`//`
`// RAM address register`	`// RAM address register`
`//`	`//`
`always @(posedge inclock)`	`always @(posedge inclock)`