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[/] [minsoc/] [trunk/] [bench/] [verilog/] [vpi/] [dbg_comm_vpi.v] - Diff between revs 2 and 71

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	`include "timescale.v"

`define JP_PORT "4567"	`define JP_PORT "4567"
`define TIMEOUT_COUNT 6'd20 // 1/2 of a TCK clock will be this many SYS_CLK ticks. Must be less than 6 bits.	`define TIMEOUT_COUNT 6'd20 // 1/2 of a TCK clock will be this many SYS_CLK ticks. Must be less than 6 bits.

`module dbg_comm_vpi (`	`module dbg_comm_vpi (`