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[/] [minsoc/] [trunk/] [prj/] [src/] [adbg_top.prj] - Diff between revs 85 and 158
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Rev 158 |
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PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
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PROJECT_DIR=rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog
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PROJECT_SRC=(adbg_wb_biu.v
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PROJECT_SRC=(adbg_crc32.v
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adbg_wb_module.v
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adbg_or1k_module.v
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adbg_wb_defines.v
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adbg_defines.v
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adbg_defines.v
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adbg_crc32.v
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adbg_jsp_biu.v
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adbg_jsp_module.v
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adbg_or1k_biu.v
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adbg_or1k_biu.v
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adbg_or1k_defines.v
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adbg_or1k_defines.v
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adbg_or1k_module.v
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adbg_or1k_status_reg.v
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adbg_or1k_status_reg.v
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adbg_top.v)
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adbg_top.v
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adbg_wb_biu.v
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adbg_wb_defines.v
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adbg_wb_module.v
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bytefifo.v
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syncflop.v
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syncreg.v)
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