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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_onchip_ram.v] - Diff between revs 2 and 6

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Rev 2	Rev 6
Line 62...	Line 62...
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//`	`//`
`// Revision History`	`// Revision History`
`//`	`//`
`//`	`//`
	`// Revision 2.1 2009/08/23 16:41:00 fajardo`
	`// Sensitivity of addr_reg and memory write changed back to posedge clk for GENERIC_MEMORY`
	`// This actually models appropriately the behavior of the FPGA internal RAMs`
	`//`
`// Revision 2.0 2009/09/10 11:30:00 fajardo`	`// Revision 2.0 2009/09/10 11:30:00 fajardo`
`// Added tri-state buffering for altera output`	`// Added tri-state buffering for altera output`
`// Sensitivity of addr_reg and memory write changed to negedge clk for GENERIC_MEMORY`	`// Sensitivity of addr_reg and memory write changed to negedge clk for GENERIC_MEMORY`
`//`	`//`
`// Revision 1.9 2009/08/18 15:15:00 fajardo`	`// Revision 1.9 2009/08/18 15:15:00 fajardo`
Line 207...	Line 211...
`assign doq = (oe) ? mem[addr_reg] : {dw{1'bZ}};`	`assign doq = (oe) ? mem[addr_reg] : {dw{1'bZ}};`

`//`	`//`
`// RAM address register`	`// RAM address register`
`//`	`//`
`always @(negedge clk or posedge rst)`	`always @(posedge clk or posedge rst)`
`if (rst)`	`if (rst)`
`addr_reg <= #1 {aw{1'b0}};`	`addr_reg <= #1 {aw{1'b0}};`
`else if (ce)`	`else if (ce)`
`addr_reg <= #1 addr;`	`addr_reg <= #1 addr;`

`//`	`//`
`// RAM write`	`// RAM write`
`//`	`//`
`always @(negedge clk)`	`always @(posedge clk)`
`if (ce && we)`	`if (ce && we)`
`mem[addr] <= #1 di;`	`mem[addr] <= #1 di;`


`elsif ARTISAN_SSP	`elsif ARTISAN_SSP

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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_onchip_ram.v] - Diff between revs 2 and 6