URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_tc_top.v] - Diff between revs 7 and 163

Rev 7	Rev 163
Line 87...	Line 87...
`// Width of WB initiator inputs (coming from WB masters)`	`// Width of WB initiator inputs (coming from WB masters)`
`//`	`//`
`// cyc + stb + address bus width +`	`// cyc + stb + address bus width +`
`// byte select bus width + we + data bus width`	`// byte select bus width + we + data bus width`
`//`	`//`
`define TC_IIN_W 1+1+1+`TC_AW+`TC_BSW+1+`TC_DW	`define TC_IIN_W 1+1+`TC_AW+`TC_BSW+1+`TC_DW

`//`	`//`
`// Traffic Cop Top`	`// Traffic Cop Top`
`//`	`//`
`module minsoc_tc_top (`	`module minsoc_tc_top (`
Line 1321...	Line 1321...
`//`	`//`
`// Register who has current access to the target.`	`// Register who has current access to the target.`
`//`	`//`
`always @(posedge wb_clk_i or posedge wb_rst_i)`	`always @(posedge wb_clk_i or posedge wb_rst_i)`
`if (wb_rst_i)`	`if (wb_rst_i)`
`req_r <= #1 3'd0;`	`req_r <= 3'd0;`
`else`	`else`
`req_r <= #1 req_won;`	`req_r <= req_won;`

`endmodule`	`endmodule`

`//`	`//`
`// Single initiator to multiple targets`	`// Single initiator to multiple targets`