Line 1... |
Line 1... |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1K test application for XESS XSV board, Top Level ////
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//// ////
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//// This file is part of the OR1K test application ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// Description ////
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//// Top level instantiating all the blocks. ////
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//// ////
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//// To Do: ////
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//// - nothing really ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: xsv_fpga_top.v,v $
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// Revision 1.10 2004/04/05 08:44:35 lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.8 2003/04/07 21:05:58 lampret
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// WB = 1/2 RISC clock test code enabled.
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//
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// Revision 1.7 2003/04/07 01:28:17 lampret
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// Adding OR1200_CLMODE_1TO2 test code.
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//
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// Revision 1.6 2002/08/12 05:35:12 lampret
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// rty_i are unused - tied to zero.
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//
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// Revision 1.5 2002/03/29 20:58:51 lampret
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// Changed hardcoded address for fake MC to use a define.
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//
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// Revision 1.4 2002/03/29 16:30:47 lampret
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// Fixed port names that changed.
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//
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// Revision 1.3 2002/03/29 15:50:03 lampret
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// Added response from memory controller (addr 0x60000000)
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//
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// Revision 1.2 2002/03/21 17:39:16 lampret
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// Fixed some typos
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//
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//
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`include "minsoc_defines.v"
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`include "minsoc_defines.v"
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module minsoc_top (
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module minsoc_top (
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clk,reset
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clk,reset
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Line 162... |
Line 90... |
assign jtag_gnd = 1'b0;
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assign jtag_gnd = 1'b0;
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`endif
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`endif
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wire rstn;
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wire rstn;
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`ifdef POSITIVE_RESET
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assign rstn = ~reset;
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assign rstn = ~reset;
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`elsif NEGATIVE_RESET
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assign rstn = reset;
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`endif
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//
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//
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// Internal wires
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// Internal wires
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//
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//
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Line 178... |
Line 110... |
wire [31:0] wb_dm_dat_o;
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wire [31:0] wb_dm_dat_o;
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wire [3:0] wb_dm_sel_o;
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wire [3:0] wb_dm_sel_o;
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wire wb_dm_we_o;
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wire wb_dm_we_o;
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wire wb_dm_stb_o;
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wire wb_dm_stb_o;
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wire wb_dm_cyc_o;
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wire wb_dm_cyc_o;
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wire wb_dm_cab_o;
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wire wb_dm_ack_i;
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wire wb_dm_ack_i;
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wire wb_dm_err_i;
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wire wb_dm_err_i;
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//
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//
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// Debug <-> RISC wires
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// Debug <-> RISC wires
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Line 210... |
Line 141... |
wire wb_rim_ack_i;
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wire wb_rim_ack_i;
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wire wb_rim_err_i;
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wire wb_rim_err_i;
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wire wb_rim_rty_i = 1'b0;
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wire wb_rim_rty_i = 1'b0;
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wire wb_rim_we_o;
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wire wb_rim_we_o;
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wire wb_rim_stb_o;
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wire wb_rim_stb_o;
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wire wb_rim_cab_o;
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wire [31:0] wb_rif_dat_i;
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wire [31:0] wb_rif_dat_i;
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wire wb_rif_ack_i;
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wire wb_rif_ack_i;
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//
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//
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// RISC data master i/f wires
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// RISC data master i/f wires
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Line 227... |
Line 157... |
wire wb_rdm_ack_i;
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wire wb_rdm_ack_i;
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wire wb_rdm_err_i;
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wire wb_rdm_err_i;
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wire wb_rdm_rty_i = 1'b0;
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wire wb_rdm_rty_i = 1'b0;
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wire wb_rdm_we_o;
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wire wb_rdm_we_o;
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wire wb_rdm_stb_o;
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wire wb_rdm_stb_o;
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wire wb_rdm_cab_o;
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//
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//
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// RISC misc
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// RISC misc
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//
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//
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wire [19:0] pic_ints;
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wire [19:0] pic_ints;
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Line 291... |
Line 220... |
wire [31:0] wb_em_dat_o;
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wire [31:0] wb_em_dat_o;
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wire [3:0] wb_em_sel_o;
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wire [3:0] wb_em_sel_o;
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wire wb_em_we_o;
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wire wb_em_we_o;
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wire wb_em_stb_o;
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wire wb_em_stb_o;
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wire wb_em_cyc_o;
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wire wb_em_cyc_o;
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wire wb_em_cab_o;
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wire wb_em_ack_i;
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wire wb_em_ack_i;
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wire wb_em_err_i;
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wire wb_em_err_i;
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//
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//
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// Ethernet core slave i/f wires
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// Ethernet core slave i/f wires
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Line 342... |
Line 270... |
reg wb_rst;
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reg wb_rst;
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//
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//
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// Global clock
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// Global clock
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//
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//
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`ifdef OR1200_CLMODE_1TO2
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reg wb_clk;
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`else
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wire wb_clk;
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wire wb_clk;
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`endif
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//
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//
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// Reset debounce
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// Reset debounce
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//
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//
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always @(posedge wb_clk or negedge rstn)
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always @(posedge wb_clk or negedge rstn)
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Line 364... |
Line 288... |
//
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//
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always @(posedge wb_clk)
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always @(posedge wb_clk)
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wb_rst <= #1 rst_r;
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wb_rst <= #1 rst_r;
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//
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//
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// This is purely for testing 1/2 WB clock
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// Clock Divider
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// This should never be used when implementing in
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// an FPGA. It is used only for simulation regressions.
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//
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//
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`ifdef OR1200_CLMODE_1TO2
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initial wb_clk = 0;
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always @(posedge clk)
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wb_clk = ~wb_clk;
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`else
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minsoc_clock_manager #
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minsoc_clock_manager #
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(
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(
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.divisor(`CLOCK_DIVISOR)
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.divisor(`CLOCK_DIVISOR)
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)
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)
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clk_adjust (
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clk_adjust (
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.clk_i(clk),
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.clk_i(clk),
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.clk_o(wb_clk)
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.clk_o(wb_clk)
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);
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);
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`endif // OR1200_CLMODE_1TO2
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//
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//
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// Unused WISHBONE signals
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// Unused WISHBONE signals
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//
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//
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assign wb_us_err_o = 1'b0;
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assign wb_us_err_o = 1'b0;
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assign wb_em_cab_o = 1'b0;
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assign wb_fs_err_o = 1'b0;
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assign wb_fs_err_o = 1'b0;
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assign wb_sp_err_o = 1'b0;
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assign wb_sp_err_o = 1'b0;
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//
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//
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// Unused interrupts
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// Unused interrupts
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Line 508... |
Line 423... |
.wb_dat_o ( wb_dm_dat_o ),
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.wb_dat_o ( wb_dm_dat_o ),
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.wb_sel_o ( wb_dm_sel_o ),
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.wb_sel_o ( wb_dm_sel_o ),
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.wb_we_o ( wb_dm_we_o ),
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.wb_we_o ( wb_dm_we_o ),
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.wb_stb_o ( wb_dm_stb_o ),
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.wb_stb_o ( wb_dm_stb_o ),
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.wb_cyc_o ( wb_dm_cyc_o ),
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.wb_cyc_o ( wb_dm_cyc_o ),
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.wb_cab_o ( wb_dm_cab_o ),
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.wb_ack_i ( wb_dm_ack_i ),
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.wb_ack_i ( wb_dm_ack_i ),
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.wb_err_i ( wb_dm_err_i ),
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.wb_err_i ( wb_dm_err_i ),
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.wb_cti_o ( ),
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.wb_cti_o ( ),
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.wb_bte_o ( ),
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.wb_bte_o ( ),
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Line 627... |
Line 541... |
.iwb_ack_i ( wb_rif_ack_i ),
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.iwb_ack_i ( wb_rif_ack_i ),
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.iwb_err_i ( wb_rim_err_i ),
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.iwb_err_i ( wb_rim_err_i ),
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.iwb_rty_i ( wb_rim_rty_i ),
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.iwb_rty_i ( wb_rim_rty_i ),
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.iwb_we_o ( wb_rim_we_o ),
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.iwb_we_o ( wb_rim_we_o ),
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.iwb_stb_o ( wb_rim_stb_o ),
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.iwb_stb_o ( wb_rim_stb_o ),
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.iwb_cab_o ( wb_rim_cab_o ),
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// WISHBONE Data Master
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// WISHBONE Data Master
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.dwb_clk_i ( wb_clk ),
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.dwb_clk_i ( wb_clk ),
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.dwb_rst_i ( wb_rst ),
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.dwb_rst_i ( wb_rst ),
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.dwb_cyc_o ( wb_rdm_cyc_o ),
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.dwb_cyc_o ( wb_rdm_cyc_o ),
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Line 642... |
Line 555... |
.dwb_ack_i ( wb_rdm_ack_i ),
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.dwb_ack_i ( wb_rdm_ack_i ),
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.dwb_err_i ( wb_rdm_err_i ),
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.dwb_err_i ( wb_rdm_err_i ),
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.dwb_rty_i ( wb_rdm_rty_i ),
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.dwb_rty_i ( wb_rdm_rty_i ),
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.dwb_we_o ( wb_rdm_we_o ),
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.dwb_we_o ( wb_rdm_we_o ),
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.dwb_stb_o ( wb_rdm_stb_o ),
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.dwb_stb_o ( wb_rdm_stb_o ),
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.dwb_cab_o ( wb_rdm_cab_o ),
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// Debug
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// Debug
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.dbg_stall_i ( dbg_stall ),
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.dbg_stall_i ( dbg_stall ),
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.dbg_dat_i ( dbg_dat_dbg ),
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.dbg_dat_i ( dbg_dat_dbg ),
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.dbg_adr_i ( dbg_adr ),
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.dbg_adr_i ( dbg_adr ),
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Line 878... |
Line 790... |
.wb_rst_i ( wb_rst ),
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.wb_rst_i ( wb_rst ),
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// WISHBONE Initiator 0
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// WISHBONE Initiator 0
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.i0_wb_cyc_i ( 1'b0 ),
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.i0_wb_cyc_i ( 1'b0 ),
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.i0_wb_stb_i ( 1'b0 ),
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.i0_wb_stb_i ( 1'b0 ),
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.i0_wb_cab_i ( 1'b0 ),
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.i0_wb_adr_i ( 32'h0000_0000 ),
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.i0_wb_adr_i ( 32'h0000_0000 ),
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.i0_wb_sel_i ( 4'b0000 ),
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.i0_wb_sel_i ( 4'b0000 ),
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.i0_wb_we_i ( 1'b0 ),
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.i0_wb_we_i ( 1'b0 ),
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.i0_wb_dat_i ( 32'h0000_0000 ),
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.i0_wb_dat_i ( 32'h0000_0000 ),
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.i0_wb_dat_o ( ),
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.i0_wb_dat_o ( ),
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Line 890... |
Line 801... |
.i0_wb_err_o ( ),
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.i0_wb_err_o ( ),
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// WISHBONE Initiator 1
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// WISHBONE Initiator 1
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.i1_wb_cyc_i ( wb_em_cyc_o ),
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.i1_wb_cyc_i ( wb_em_cyc_o ),
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.i1_wb_stb_i ( wb_em_stb_o ),
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.i1_wb_stb_i ( wb_em_stb_o ),
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.i1_wb_cab_i ( wb_em_cab_o ),
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.i1_wb_adr_i ( wb_em_adr_o ),
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.i1_wb_adr_i ( wb_em_adr_o ),
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.i1_wb_sel_i ( wb_em_sel_o ),
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.i1_wb_sel_i ( wb_em_sel_o ),
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.i1_wb_we_i ( wb_em_we_o ),
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.i1_wb_we_i ( wb_em_we_o ),
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.i1_wb_dat_i ( wb_em_dat_o ),
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.i1_wb_dat_i ( wb_em_dat_o ),
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.i1_wb_dat_o ( wb_em_dat_i ),
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.i1_wb_dat_o ( wb_em_dat_i ),
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Line 902... |
Line 812... |
.i1_wb_err_o ( wb_em_err_i ),
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.i1_wb_err_o ( wb_em_err_i ),
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// WISHBONE Initiator 2
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// WISHBONE Initiator 2
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.i2_wb_cyc_i ( 1'b0 ),
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.i2_wb_cyc_i ( 1'b0 ),
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.i2_wb_stb_i ( 1'b0 ),
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.i2_wb_stb_i ( 1'b0 ),
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.i2_wb_cab_i ( 1'b0 ),
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.i2_wb_adr_i ( 32'h0000_0000 ),
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.i2_wb_adr_i ( 32'h0000_0000 ),
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.i2_wb_sel_i ( 4'b0000 ),
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.i2_wb_sel_i ( 4'b0000 ),
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.i2_wb_we_i ( 1'b0 ),
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.i2_wb_we_i ( 1'b0 ),
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.i2_wb_dat_i ( 32'h0000_0000 ),
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.i2_wb_dat_i ( 32'h0000_0000 ),
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.i2_wb_dat_o ( ),
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.i2_wb_dat_o ( ),
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Line 914... |
Line 823... |
.i2_wb_err_o ( ),
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.i2_wb_err_o ( ),
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// WISHBONE Initiator 3
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// WISHBONE Initiator 3
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.i3_wb_cyc_i ( wb_dm_cyc_o ),
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.i3_wb_cyc_i ( wb_dm_cyc_o ),
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.i3_wb_stb_i ( wb_dm_stb_o ),
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.i3_wb_stb_i ( wb_dm_stb_o ),
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.i3_wb_cab_i ( wb_dm_cab_o ),
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.i3_wb_adr_i ( wb_dm_adr_o ),
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.i3_wb_adr_i ( wb_dm_adr_o ),
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.i3_wb_sel_i ( wb_dm_sel_o ),
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.i3_wb_sel_i ( wb_dm_sel_o ),
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.i3_wb_we_i ( wb_dm_we_o ),
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.i3_wb_we_i ( wb_dm_we_o ),
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.i3_wb_dat_i ( wb_dm_dat_o ),
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.i3_wb_dat_i ( wb_dm_dat_o ),
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.i3_wb_dat_o ( wb_dm_dat_i ),
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.i3_wb_dat_o ( wb_dm_dat_i ),
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Line 926... |
Line 834... |
.i3_wb_err_o ( wb_dm_err_i ),
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.i3_wb_err_o ( wb_dm_err_i ),
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|
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// WISHBONE Initiator 4
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// WISHBONE Initiator 4
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.i4_wb_cyc_i ( wb_rdm_cyc_o ),
|
.i4_wb_cyc_i ( wb_rdm_cyc_o ),
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.i4_wb_stb_i ( wb_rdm_stb_o ),
|
.i4_wb_stb_i ( wb_rdm_stb_o ),
|
.i4_wb_cab_i ( wb_rdm_cab_o ),
|
|
.i4_wb_adr_i ( wb_rdm_adr_o ),
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.i4_wb_adr_i ( wb_rdm_adr_o ),
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.i4_wb_sel_i ( wb_rdm_sel_o ),
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.i4_wb_sel_i ( wb_rdm_sel_o ),
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.i4_wb_we_i ( wb_rdm_we_o ),
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.i4_wb_we_i ( wb_rdm_we_o ),
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.i4_wb_dat_i ( wb_rdm_dat_o ),
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.i4_wb_dat_i ( wb_rdm_dat_o ),
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.i4_wb_dat_o ( wb_rdm_dat_i ),
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.i4_wb_dat_o ( wb_rdm_dat_i ),
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Line 938... |
Line 845... |
.i4_wb_err_o ( wb_rdm_err_i ),
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.i4_wb_err_o ( wb_rdm_err_i ),
|
|
|
// WISHBONE Initiator 5
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// WISHBONE Initiator 5
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.i5_wb_cyc_i ( wb_rim_cyc_o ),
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.i5_wb_cyc_i ( wb_rim_cyc_o ),
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.i5_wb_stb_i ( wb_rim_stb_o ),
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.i5_wb_stb_i ( wb_rim_stb_o ),
|
.i5_wb_cab_i ( wb_rim_cab_o ),
|
|
.i5_wb_adr_i ( wb_rim_adr_o ),
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.i5_wb_adr_i ( wb_rim_adr_o ),
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.i5_wb_sel_i ( wb_rim_sel_o ),
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.i5_wb_sel_i ( wb_rim_sel_o ),
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.i5_wb_we_i ( wb_rim_we_o ),
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.i5_wb_we_i ( wb_rim_we_o ),
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.i5_wb_dat_i ( wb_rim_dat_o ),
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.i5_wb_dat_i ( wb_rim_dat_o ),
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.i5_wb_dat_o ( wb_rim_dat_i ),
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.i5_wb_dat_o ( wb_rim_dat_i ),
|
Line 950... |
Line 856... |
.i5_wb_err_o ( wb_rim_err_i ),
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.i5_wb_err_o ( wb_rim_err_i ),
|
|
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// WISHBONE Initiator 6
|
// WISHBONE Initiator 6
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.i6_wb_cyc_i ( 1'b0 ),
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.i6_wb_cyc_i ( 1'b0 ),
|
.i6_wb_stb_i ( 1'b0 ),
|
.i6_wb_stb_i ( 1'b0 ),
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.i6_wb_cab_i ( 1'b0 ),
|
|
.i6_wb_adr_i ( 32'h0000_0000 ),
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.i6_wb_adr_i ( 32'h0000_0000 ),
|
.i6_wb_sel_i ( 4'b0000 ),
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.i6_wb_sel_i ( 4'b0000 ),
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.i6_wb_we_i ( 1'b0 ),
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.i6_wb_we_i ( 1'b0 ),
|
.i6_wb_dat_i ( 32'h0000_0000 ),
|
.i6_wb_dat_i ( 32'h0000_0000 ),
|
.i6_wb_dat_o ( ),
|
.i6_wb_dat_o ( ),
|
Line 962... |
Line 867... |
.i6_wb_err_o ( ),
|
.i6_wb_err_o ( ),
|
|
|
// WISHBONE Initiator 7
|
// WISHBONE Initiator 7
|
.i7_wb_cyc_i ( 1'b0 ),
|
.i7_wb_cyc_i ( 1'b0 ),
|
.i7_wb_stb_i ( 1'b0 ),
|
.i7_wb_stb_i ( 1'b0 ),
|
.i7_wb_cab_i ( 1'b0 ),
|
|
.i7_wb_adr_i ( 32'h0000_0000 ),
|
.i7_wb_adr_i ( 32'h0000_0000 ),
|
.i7_wb_sel_i ( 4'b0000 ),
|
.i7_wb_sel_i ( 4'b0000 ),
|
.i7_wb_we_i ( 1'b0 ),
|
.i7_wb_we_i ( 1'b0 ),
|
.i7_wb_dat_i ( 32'h0000_0000 ),
|
.i7_wb_dat_i ( 32'h0000_0000 ),
|
.i7_wb_dat_o ( ),
|
.i7_wb_dat_o ( ),
|
Line 974... |
Line 878... |
.i7_wb_err_o ( ),
|
.i7_wb_err_o ( ),
|
|
|
// WISHBONE Target 0
|
// WISHBONE Target 0
|
.t0_wb_cyc_o ( wb_ss_cyc_i ),
|
.t0_wb_cyc_o ( wb_ss_cyc_i ),
|
.t0_wb_stb_o ( wb_ss_stb_i ),
|
.t0_wb_stb_o ( wb_ss_stb_i ),
|
.t0_wb_cab_o ( wb_ss_cab_i ),
|
|
.t0_wb_adr_o ( wb_ss_adr_i ),
|
.t0_wb_adr_o ( wb_ss_adr_i ),
|
.t0_wb_sel_o ( wb_ss_sel_i ),
|
.t0_wb_sel_o ( wb_ss_sel_i ),
|
.t0_wb_we_o ( wb_ss_we_i ),
|
.t0_wb_we_o ( wb_ss_we_i ),
|
.t0_wb_dat_o ( wb_ss_dat_i ),
|
.t0_wb_dat_o ( wb_ss_dat_i ),
|
.t0_wb_dat_i ( wb_ss_dat_o ),
|
.t0_wb_dat_i ( wb_ss_dat_o ),
|
Line 986... |
Line 889... |
.t0_wb_err_i ( wb_ss_err_o ),
|
.t0_wb_err_i ( wb_ss_err_o ),
|
|
|
// WISHBONE Target 1
|
// WISHBONE Target 1
|
.t1_wb_cyc_o ( wb_fs_cyc_i ),
|
.t1_wb_cyc_o ( wb_fs_cyc_i ),
|
.t1_wb_stb_o ( wb_fs_stb_i ),
|
.t1_wb_stb_o ( wb_fs_stb_i ),
|
.t1_wb_cab_o ( wb_fs_cab_i ),
|
|
.t1_wb_adr_o ( wb_fs_adr_i ),
|
.t1_wb_adr_o ( wb_fs_adr_i ),
|
.t1_wb_sel_o ( wb_fs_sel_i ),
|
.t1_wb_sel_o ( wb_fs_sel_i ),
|
.t1_wb_we_o ( wb_fs_we_i ),
|
.t1_wb_we_o ( wb_fs_we_i ),
|
.t1_wb_dat_o ( wb_fs_dat_i ),
|
.t1_wb_dat_o ( wb_fs_dat_i ),
|
.t1_wb_dat_i ( wb_fs_dat_o ),
|
.t1_wb_dat_i ( wb_fs_dat_o ),
|
Line 998... |
Line 900... |
.t1_wb_err_i ( wb_fs_err_o ),
|
.t1_wb_err_i ( wb_fs_err_o ),
|
|
|
// WISHBONE Target 2
|
// WISHBONE Target 2
|
.t2_wb_cyc_o ( wb_sp_cyc_i ),
|
.t2_wb_cyc_o ( wb_sp_cyc_i ),
|
.t2_wb_stb_o ( wb_sp_stb_i ),
|
.t2_wb_stb_o ( wb_sp_stb_i ),
|
.t2_wb_cab_o ( wb_sp_cab_i ),
|
|
.t2_wb_adr_o ( wb_sp_adr_i ),
|
.t2_wb_adr_o ( wb_sp_adr_i ),
|
.t2_wb_sel_o ( wb_sp_sel_i ),
|
.t2_wb_sel_o ( wb_sp_sel_i ),
|
.t2_wb_we_o ( wb_sp_we_i ),
|
.t2_wb_we_o ( wb_sp_we_i ),
|
.t2_wb_dat_o ( wb_sp_dat_i ),
|
.t2_wb_dat_o ( wb_sp_dat_i ),
|
.t2_wb_dat_i ( wb_sp_dat_o ),
|
.t2_wb_dat_i ( wb_sp_dat_o ),
|
Line 1010... |
Line 911... |
.t2_wb_err_i ( wb_sp_err_o ),
|
.t2_wb_err_i ( wb_sp_err_o ),
|
|
|
// WISHBONE Target 3
|
// WISHBONE Target 3
|
.t3_wb_cyc_o ( wb_es_cyc_i ),
|
.t3_wb_cyc_o ( wb_es_cyc_i ),
|
.t3_wb_stb_o ( wb_es_stb_i ),
|
.t3_wb_stb_o ( wb_es_stb_i ),
|
.t3_wb_cab_o ( wb_es_cab_i ),
|
|
.t3_wb_adr_o ( wb_es_adr_i ),
|
.t3_wb_adr_o ( wb_es_adr_i ),
|
.t3_wb_sel_o ( wb_es_sel_i ),
|
.t3_wb_sel_o ( wb_es_sel_i ),
|
.t3_wb_we_o ( wb_es_we_i ),
|
.t3_wb_we_o ( wb_es_we_i ),
|
.t3_wb_dat_o ( wb_es_dat_i ),
|
.t3_wb_dat_o ( wb_es_dat_i ),
|
.t3_wb_dat_i ( wb_es_dat_o ),
|
.t3_wb_dat_i ( wb_es_dat_o ),
|
Line 1022... |
Line 922... |
.t3_wb_err_i ( wb_es_err_o ),
|
.t3_wb_err_i ( wb_es_err_o ),
|
|
|
// WISHBONE Target 4
|
// WISHBONE Target 4
|
.t4_wb_cyc_o ( ),
|
.t4_wb_cyc_o ( ),
|
.t4_wb_stb_o ( ),
|
.t4_wb_stb_o ( ),
|
.t4_wb_cab_o ( ),
|
|
.t4_wb_adr_o ( ),
|
.t4_wb_adr_o ( ),
|
.t4_wb_sel_o ( ),
|
.t4_wb_sel_o ( ),
|
.t4_wb_we_o ( ),
|
.t4_wb_we_o ( ),
|
.t4_wb_dat_o ( ),
|
.t4_wb_dat_o ( ),
|
.t4_wb_dat_i ( 32'h0000_0000 ),
|
.t4_wb_dat_i ( 32'h0000_0000 ),
|
Line 1034... |
Line 933... |
.t4_wb_err_i ( 1'b1 ),
|
.t4_wb_err_i ( 1'b1 ),
|
|
|
// WISHBONE Target 5
|
// WISHBONE Target 5
|
.t5_wb_cyc_o ( wb_us_cyc_i ),
|
.t5_wb_cyc_o ( wb_us_cyc_i ),
|
.t5_wb_stb_o ( wb_us_stb_i ),
|
.t5_wb_stb_o ( wb_us_stb_i ),
|
.t5_wb_cab_o ( wb_us_cab_i ),
|
|
.t5_wb_adr_o ( wb_us_adr_i ),
|
.t5_wb_adr_o ( wb_us_adr_i ),
|
.t5_wb_sel_o ( wb_us_sel_i ),
|
.t5_wb_sel_o ( wb_us_sel_i ),
|
.t5_wb_we_o ( wb_us_we_i ),
|
.t5_wb_we_o ( wb_us_we_i ),
|
.t5_wb_dat_o ( wb_us_dat_i ),
|
.t5_wb_dat_o ( wb_us_dat_i ),
|
.t5_wb_dat_i ( wb_us_dat_o ),
|
.t5_wb_dat_i ( wb_us_dat_o ),
|
Line 1046... |
Line 944... |
.t5_wb_err_i ( wb_us_err_o ),
|
.t5_wb_err_i ( wb_us_err_o ),
|
|
|
// WISHBONE Target 6
|
// WISHBONE Target 6
|
.t6_wb_cyc_o ( ),
|
.t6_wb_cyc_o ( ),
|
.t6_wb_stb_o ( ),
|
.t6_wb_stb_o ( ),
|
.t6_wb_cab_o ( ),
|
|
.t6_wb_adr_o ( ),
|
.t6_wb_adr_o ( ),
|
.t6_wb_sel_o ( ),
|
.t6_wb_sel_o ( ),
|
.t6_wb_we_o ( ),
|
.t6_wb_we_o ( ),
|
.t6_wb_dat_o ( ),
|
.t6_wb_dat_o ( ),
|
.t6_wb_dat_i ( 32'h0000_0000 ),
|
.t6_wb_dat_i ( 32'h0000_0000 ),
|
Line 1058... |
Line 955... |
.t6_wb_err_i ( 1'b1 ),
|
.t6_wb_err_i ( 1'b1 ),
|
|
|
// WISHBONE Target 7
|
// WISHBONE Target 7
|
.t7_wb_cyc_o ( ),
|
.t7_wb_cyc_o ( ),
|
.t7_wb_stb_o ( ),
|
.t7_wb_stb_o ( ),
|
.t7_wb_cab_o ( ),
|
|
.t7_wb_adr_o ( ),
|
.t7_wb_adr_o ( ),
|
.t7_wb_sel_o ( ),
|
.t7_wb_sel_o ( ),
|
.t7_wb_we_o ( ),
|
.t7_wb_we_o ( ),
|
.t7_wb_dat_o ( ),
|
.t7_wb_dat_o ( ),
|
.t7_wb_dat_i ( 32'h0000_0000 ),
|
.t7_wb_dat_i ( 32'h0000_0000 ),
|
Line 1070... |
Line 966... |
.t7_wb_err_i ( 1'b1 ),
|
.t7_wb_err_i ( 1'b1 ),
|
|
|
// WISHBONE Target 8
|
// WISHBONE Target 8
|
.t8_wb_cyc_o ( ),
|
.t8_wb_cyc_o ( ),
|
.t8_wb_stb_o ( ),
|
.t8_wb_stb_o ( ),
|
.t8_wb_cab_o ( ),
|
|
.t8_wb_adr_o ( ),
|
.t8_wb_adr_o ( ),
|
.t8_wb_sel_o ( ),
|
.t8_wb_sel_o ( ),
|
.t8_wb_we_o ( ),
|
.t8_wb_we_o ( ),
|
.t8_wb_dat_o ( ),
|
.t8_wb_dat_o ( ),
|
.t8_wb_dat_i ( 32'h0000_0000 ),
|
.t8_wb_dat_i ( 32'h0000_0000 ),
|