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Line 1... |
`include "minsoc_defines.v"
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`include "minsoc_defines.v"
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`include "interconnect_defines.v"
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`include "or1200_defines.v"
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`include "or1200_defines.v"
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module minsoc_top (
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module minsoc_top (
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clk,reset
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clk,reset
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Line 115... |
wire wb_dm_cyc_o;
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wire wb_dm_cyc_o;
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wire wb_dm_ack_i;
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wire wb_dm_ack_i;
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wire wb_dm_err_i;
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wire wb_dm_err_i;
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//
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//
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// Debug core JSP slave i/f wires
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//
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wire [31:0] wb_jsp_dat_i;
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wire [31:0] wb_jsp_dat_o;
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wire [31:0] wb_jsp_adr_i;
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wire [3:0] wb_jsp_sel_i;
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wire wb_jsp_we_i;
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wire wb_jsp_cyc_i;
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wire wb_jsp_stb_i;
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wire wb_jsp_ack_o;
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wire wb_jsp_err_o;
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//
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// Debug <-> RISC wires
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// Debug <-> RISC wires
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//
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//
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wire [3:0] dbg_lss;
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wire [3:0] dbg_lss;
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wire [1:0] dbg_is;
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wire [1:0] dbg_is;
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wire [10:0] dbg_wp;
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wire [10:0] dbg_wp;
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| Line 301... |
Line 315... |
.clk_i(clk),
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.clk_i(clk),
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.clk_o(wb_clk)
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.clk_o(wb_clk)
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);
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);
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//
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//
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// Unused WISHBONE signals
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//
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assign wb_us_err_o = 1'b0;
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assign wb_fs_err_o = 1'b0;
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assign wb_sp_err_o = 1'b0;
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//
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// Unused interrupts
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// Unused interrupts
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//
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//
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assign pic_ints[`APP_INT_RES1] = 'b0;
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assign pic_ints[`APP_INT_RES1] = 'b0;
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assign pic_ints[`APP_INT_RES2] = 'b0;
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assign pic_ints[`APP_INT_RES2] = 'b0;
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assign pic_ints[`APP_INT_RES3] = 'b0;
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assign pic_ints[`APP_INT_RES3] = 'b0;
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| Line 443... |
Line 450... |
.cpu0_bp_i ( (dbg_bp | (| dbg_wp[10:0])) ),
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.cpu0_bp_i ( (dbg_bp | (| dbg_wp[10:0])) ),
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.cpu0_stall_o( dbg_stall ),
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.cpu0_stall_o( dbg_stall ),
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.cpu0_stb_o ( dbg_stb ),
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.cpu0_stb_o ( dbg_stb ),
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.cpu0_we_o ( dbg_we ),
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.cpu0_we_o ( dbg_we ),
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.cpu0_ack_i ( dbg_ack ),
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.cpu0_ack_i ( dbg_ack ),
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.cpu0_rst_o ( )
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.cpu0_rst_o ( ),
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// WISHBONE slave interface (JTAG UART)
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`ifdef JSP
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.wb_jsp_adr_i ( wb_jsp_adr_i[31:0] ),
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.wb_jsp_dat_i ( wb_jsp_dat_i[31:0] ),
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.wb_jsp_dat_o ( wb_jsp_dat_o[31:0] ),
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.wb_jsp_we_i ( wb_jsp_we_i ),
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.wb_jsp_stb_i ( wb_jsp_stb_i ),
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.wb_jsp_cyc_i ( wb_jsp_cyc_i ),
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.wb_jsp_ack_o ( wb_jsp_ack_o ),
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.wb_jsp_sel_i ( wb_jsp_sel_i[3:0] ),
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.wb_jsp_cab_i ( 1'b0 ),
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.wb_jsp_cti_i ( 3'b0 ),
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.wb_jsp_bte_i ( 2'b0 ),
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// Interrupt request
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.int_o ( pic_ints[`APP_INT_JSP] )
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`else
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.wb_jsp_adr_i ( 32'h0000_0000 ),
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.wb_jsp_dat_i ( 32'h0000_0000 ),
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.wb_jsp_dat_o ( ),
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.wb_jsp_we_i ( 1'b0 ),
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.wb_jsp_stb_i ( 1'b0 ),
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.wb_jsp_cyc_i ( 1'b0 ),
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.wb_jsp_ack_o ( ),
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.wb_jsp_sel_i ( 4'h0 ),
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.wb_jsp_cab_i ( 1'b0 ),
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.wb_jsp_cti_i ( 3'b0 ),
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.wb_jsp_bte_i ( 2'b0 ),
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// Interrupt request
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.int_o ( )
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`endif
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);
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);
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`ifdef JSP
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assign wb_jsp_err_o = 1'b0;
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`else
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assign wb_jsp_dat_o = 32'h0000_0000;
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assign wb_jsp_ack_o = 1'b0;
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assign wb_jsp_err_o = 1'b1;
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assign pic_ints[`APP_INT_JSP] = 1'b0;
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`endif
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//
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//
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// JTAG TAP controller instantiation
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// JTAG TAP controller instantiation
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//
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//
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`ifdef GENERIC_TAP
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`ifdef GENERIC_TAP
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tap_top tap_top(
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tap_top tap_top(
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| Line 629... |
Line 678... |
.mosi_pad_o(spi_flash_mosi),
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.mosi_pad_o(spi_flash_mosi),
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.miso_pad_i(spi_flash_miso),
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.miso_pad_i(spi_flash_miso),
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.sclk_pad_o(spi_flash_sclk),
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.sclk_pad_o(spi_flash_sclk),
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.ss_pad_o(spi_flash_ss)
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.ss_pad_o(spi_flash_ss)
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);
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);
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assign wb_fs_err_o = 1'b0;
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assign wb_sp_err_o = 1'b0;
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`else
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`else
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assign wb_fs_dat_o = 32'h0000_0000;
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assign wb_fs_dat_o = 32'h0000_0000;
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assign wb_fs_ack_o = 1'b0;
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assign wb_fs_ack_o = 1'b0;
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assign wb_fs_err_o = 1'b1;
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assign wb_sp_dat_o = 32'h0000_0000;
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assign wb_sp_dat_o = 32'h0000_0000;
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assign wb_sp_ack_o = 1'b0;
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assign wb_sp_ack_o = 1'b0;
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assign wb_sp_err_o = 1'b1;
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`endif
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`endif
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//
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//
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// Instantiation of the SRAM controller
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// Instantiation of the SRAM controller
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//
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//
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Line 756... |
.dtr_pad_o ( ),
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.dtr_pad_o ( ),
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.dsr_pad_i ( 1'b0 ),
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.dsr_pad_i ( 1'b0 ),
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.ri_pad_i ( 1'b0 ),
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.ri_pad_i ( 1'b0 ),
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.dcd_pad_i ( 1'b0 )
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.dcd_pad_i ( 1'b0 )
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);
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);
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assign wb_us_err_o = 1'b0;
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`else
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`else
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assign wb_us_dat_o = 32'h0000_0000;
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assign wb_us_dat_o = 32'h0000_0000;
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assign wb_us_ack_o = 1'b0;
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assign wb_us_ack_o = 1'b0;
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assign wb_us_err_o = 1'b1;
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assign pic_ints[`APP_INT_UART] = 1'b0;
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assign pic_ints[`APP_INT_UART] = 1'b0;
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`endif
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`endif
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//
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//
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Line 824... |
.int_o ( pic_ints[`APP_INT_ETH] )
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.int_o ( pic_ints[`APP_INT_ETH] )
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);
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);
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`else
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`else
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assign wb_es_dat_o = 32'h0000_0000;
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assign wb_es_dat_o = 32'h0000_0000;
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assign wb_es_ack_o = 1'b0;
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assign wb_es_ack_o = 1'b0;
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assign wb_es_err_o = 1'b0;
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assign wb_es_err_o = 1'b1;
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assign wb_em_adr_o = 32'h0000_0000;
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assign wb_em_adr_o = 32'h0000_0000;
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assign wb_em_sel_o = 4'h0;
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assign wb_em_sel_o = 4'h0;
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assign wb_em_we_o = 1'b0;
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assign wb_em_we_o = 1'b0;
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assign wb_em_dat_o = 32'h0000_0000;
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assign wb_em_dat_o = 32'h0000_0000;
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| Line 793... |
Line 851... |
`APP_ADDR_SPI,
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`APP_ADDR_SPI,
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`APP_ADDR_ETH,
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`APP_ADDR_ETH,
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`APP_ADDR_AUDIO,
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`APP_ADDR_AUDIO,
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`APP_ADDR_UART,
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`APP_ADDR_UART,
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`APP_ADDR_PS2,
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`APP_ADDR_PS2,
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`APP_ADDR_RES1,
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`APP_ADDR_JSP,
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`APP_ADDR_RES2
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`APP_ADDR_RES2
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) tc_top (
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) tc_top (
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// WISHBONE common
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// WISHBONE common
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.wb_clk_i ( wb_clk ),
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.wb_clk_i ( wb_clk ),
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| Line 967... |
Line 1025... |
.t6_wb_dat_i ( 32'h0000_0000 ),
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.t6_wb_dat_i ( 32'h0000_0000 ),
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.t6_wb_ack_i ( 1'b0 ),
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.t6_wb_ack_i ( 1'b0 ),
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.t6_wb_err_i ( 1'b1 ),
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.t6_wb_err_i ( 1'b1 ),
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// WISHBONE Target 7
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// WISHBONE Target 7
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.t7_wb_cyc_o ( ),
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.t7_wb_cyc_o ( wb_jsp_cyc_i ),
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.t7_wb_stb_o ( ),
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.t7_wb_stb_o ( wb_jsp_stb_i ),
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.t7_wb_adr_o ( ),
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.t7_wb_adr_o ( wb_jsp_adr_i ),
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.t7_wb_sel_o ( ),
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.t7_wb_sel_o ( wb_jsp_sel_i ),
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.t7_wb_we_o ( ),
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.t7_wb_we_o ( wb_jsp_we_i ),
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.t7_wb_dat_o ( ),
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.t7_wb_dat_o ( wb_jsp_dat_i ),
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.t7_wb_dat_i ( 32'h0000_0000 ),
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.t7_wb_dat_i ( wb_jsp_dat_o ),
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.t7_wb_ack_i ( 1'b0 ),
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.t7_wb_ack_i ( wb_jsp_ack_o ),
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.t7_wb_err_i ( 1'b1 ),
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.t7_wb_err_i ( wb_jsp_err_o ),
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// WISHBONE Target 8
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// WISHBONE Target 8
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.t8_wb_cyc_o ( ),
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.t8_wb_cyc_o ( ),
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.t8_wb_stb_o ( ),
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.t8_wb_stb_o ( ),
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.t8_wb_adr_o ( ),
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.t8_wb_adr_o ( ),
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