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https://opencores.org/ocsvn/minsoc/minsoc/trunk
[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_top.v] - Diff between revs 16 and 17
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| Rev 16 |
Rev 17 |
| Line 695... |
Line 695... |
.dcd_pad_i ( 1'b0 )
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.dcd_pad_i ( 1'b0 )
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);
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);
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`else
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`else
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assign wb_us_dat_o = 32'h0000_0000;
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assign wb_us_dat_o = 32'h0000_0000;
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assign wb_us_ack_o = 1'b0;
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assign wb_us_ack_o = 1'b0;
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assign pic_ints[`APP_INT_UART] = 1'b0;
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assign pic_ints[`APP_INT_UART] = 1'b0;
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`endif
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`endif
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//
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//
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// Instantiation of the Ethernet 10/100 MAC
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// Instantiation of the Ethernet 10/100 MAC
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| Line 764... |
Line 765... |
assign wb_em_sel_o = 4'h0;
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assign wb_em_sel_o = 4'h0;
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assign wb_em_we_o = 1'b0;
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assign wb_em_we_o = 1'b0;
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assign wb_em_dat_o = 32'h0000_0000;
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assign wb_em_dat_o = 32'h0000_0000;
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assign wb_em_cyc_o = 1'b0;
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assign wb_em_cyc_o = 1'b0;
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assign wb_em_stb_o = 1'b0;
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assign wb_em_stb_o = 1'b0;
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assign pic_ints[`APP_INT_ETH] = 1'b0;
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assign pic_ints[`APP_INT_ETH] = 1'b0;
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`endif
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`endif
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//
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//
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// Instantiation of the Traffic COP
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// Instantiation of the Traffic COP
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