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https://opencores.org/ocsvn/minsoc/minsoc/trunk
[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_top.v] - Diff between revs 17 and 20
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| Rev 17 |
Rev 20 |
| Line 125... |
Line 125... |
wire [31:0] dbg_dat_dbg;
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wire [31:0] dbg_dat_dbg;
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wire [31:0] dbg_dat_risc;
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wire [31:0] dbg_dat_risc;
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wire [31:0] dbg_adr;
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wire [31:0] dbg_adr;
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wire dbg_ewt;
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wire dbg_ewt;
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wire dbg_stall;
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wire dbg_stall;
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wire [2:0] dbg_op; //dbg_op[0] = dbg_we //dbg_op[2] = dbg_stb (didn't change for backward compatibility with DBG_IF_MODEL
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wire dbg_we;
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wire dbg_stb;
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wire dbg_ack;
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wire dbg_ack;
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//
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//
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// RISC instruction master i/f wires
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// RISC instruction master i/f wires
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//
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//
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| Line 435... |
Line 436... |
.cpu0_addr_o ( dbg_adr ),
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.cpu0_addr_o ( dbg_adr ),
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.cpu0_data_i ( dbg_dat_risc ),
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.cpu0_data_i ( dbg_dat_risc ),
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.cpu0_data_o ( dbg_dat_dbg ),
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.cpu0_data_o ( dbg_dat_dbg ),
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.cpu0_bp_i ( dbg_bp ),
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.cpu0_bp_i ( dbg_bp ),
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.cpu0_stall_o( dbg_stall ),
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.cpu0_stall_o( dbg_stall ),
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.cpu0_stb_o ( dbg_op[2] ),
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.cpu0_stb_o ( dbg_stb ),
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.cpu0_we_o ( dbg_op[0] ),
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.cpu0_we_o ( dbg_we ),
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.cpu0_ack_i ( dbg_ack ),
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.cpu0_ack_i ( dbg_ack ),
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.cpu0_rst_o ( )
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.cpu0_rst_o ( )
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);
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);
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| Line 567... |
Line 568... |
.dbg_is_o ( dbg_is ),
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.dbg_is_o ( dbg_is ),
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.dbg_wp_o ( dbg_wp ),
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.dbg_wp_o ( dbg_wp ),
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.dbg_bp_o ( dbg_bp ),
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.dbg_bp_o ( dbg_bp ),
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.dbg_dat_o ( dbg_dat_risc ),
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.dbg_dat_o ( dbg_dat_risc ),
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.dbg_ack_o ( dbg_ack ),
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.dbg_ack_o ( dbg_ack ),
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.dbg_stb_i ( dbg_op[2] ),
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.dbg_stb_i ( dbg_stb ),
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.dbg_we_i ( dbg_op[0] ),
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.dbg_we_i ( dbg_we ),
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// Power Management
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// Power Management
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.pm_clksd_o ( ),
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.pm_clksd_o ( ),
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.pm_cpustall_i ( 1'b0 ),
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.pm_cpustall_i ( 1'b0 ),
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.pm_dc_gate_o ( ),
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.pm_dc_gate_o ( ),
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