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[/] [minsoc/] [trunk/] [rtl/] [verilog/] [minsoc_top.v] - Diff between revs 20 and 26
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| Rev 20 |
Rev 26 |
| Line 482... |
Line 482... |
);
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);
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`elsif FPGA_TAP
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`elsif FPGA_TAP
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`ifdef ALTERA_FPGA
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`ifdef ALTERA_FPGA
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altera_virtual_jtag tap_top(
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altera_virtual_jtag tap_top(
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.tck_o(jtag_tck),
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.tck_o(jtag_tck),
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.debug_tdo_o(debug_tdo),
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.debug_tdo_i(debug_tdo),
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.tdi_o(debug_tdi),
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.tdi_o(debug_tdi),
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.test_logic_reset_o(test_logic_reset),
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.test_logic_reset_o(test_logic_reset),
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.run_test_idle_o(),
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.run_test_idle_o(),
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.shift_dr_o(shift_dr),
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.shift_dr_o(shift_dr),
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.capture_dr_o(capture_dr),
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.capture_dr_o(capture_dr),
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