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Line 7... |
DEBUG_RTL = ${ADV_DEBUG_ROOT}/adv_dbg_if/rtl/verilog
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DEBUG_RTL = ${ADV_DEBUG_ROOT}/adv_dbg_if/rtl/verilog
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OR1200_RTL = ${MINSOC_RTL}/or1200/rtl/verilog
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OR1200_RTL = ${MINSOC_RTL}/or1200/rtl/verilog
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ETH_RTL = ${MINSOC_RTL}/ethmac/rtl/verilog
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ETH_RTL = ${MINSOC_RTL}/ethmac/rtl/verilog
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BUILD_SUPPORT = $(MINSOC)/syn/buildSupport
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BUILD_SUPPORT = $(MINSOC)/syn/buildSupport
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PROJECT_DIR = $(MINSOC)/prj/altera
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PROJECT_DIR = $(MINSOC)/prj/altera
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QSF_FILE = $(BUILD_SUPPORT)/minsoc_top
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help:
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help:
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@echo " all: Synthesize and implement the SoC, then generate a bit stream"
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@echo " all: Synthesize and implement the SoC, then generate a bit stream"
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@echo ""
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@echo ""
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@echo " bitgen: Generate a programming file for the target FPGA"
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@echo " bitgen: Generate a programming file for the target FPGA"
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@echo " map: Express the SoC netlist in the target hardware"
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@echo " map: Express the SoC netlist in the target hardware"
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@echo " fit: Place the target hardware, then route the wires"
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@echo " fit: Place the target hardware, then route the wires"
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@echo " sta: Perfom a timming analysis"
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@echo " sta: Perfom a timming analysis"
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@echo " eda: Generate a netlist of the hardware"
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@echo " eda: Generate a netlist of the hardware"
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@echo " config: Load the bitstream into the device using ALTERA USB Blaster and JTAG configuration"
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@echo ""
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@echo ""
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@echo " clean: Delete all superfluous files generated by Altera tools"
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@echo " clean: Delete all superfluous files generated by Altera tools"
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@echo " distclean: Delete all generated files"
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@echo " distclean: Delete all generated files"
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all: bitgen eda sta
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all: bitgen eda sta
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map: minsoc_top.map.summary
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map: $(BUILD_SUPPORT)/minsoc_top.map.summary
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fit: minsoc_top.fit.summary
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fit: $(BUILD_SUPPORT)/minsoc_top.fit.summary
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bitgen: minsoc_top.sof
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bitgen: minsoc_top.sof
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eda: minsoc_top.eda.summary
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eda: $(BUILD_SUPPORT)/minsoc_top.eda.summary
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sta: minsoc_top.sta.summary
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sta: $(BUILD_SUPPORT)/minsoc_top.sta.summary
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#minsoc_top.map.summary: ${MINSOC_RTL}/*.v $(UART_RTL)/*.v $(ADV_DEBUG_ROOT)/*.v $(DEBUG_RTL)/*.v $(OR1200_RTL)/*.v $(ETH_RTL)/*.v ${MINSOC_DEFINES}/minsoc_defines.v minsoc_top.qsf
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#minsoc_top.map.summary: ${MINSOC_RTL}/*.v $(UART_RTL)/*.v $(ADV_DEBUG_ROOT)/*.v $(DEBUG_RTL)/*.v $(OR1200_RTL)/*.v $(ETH_RTL)/*.v ${MINSOC_DEFINES}/minsoc_defines.v minsoc_top.qsf
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minsoc_top.map.summary: ${MINSOC_DEFINES}/minsoc_defines.v minsoc_top.qsf
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$(BUILD_SUPPORT)/minsoc_top.map.summary: ${MINSOC_DEFINES}/minsoc_defines.v $(BUILD_SUPPORT)/minsoc_top.qsf
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quartus_map $(QSF_FILE) --write_settings_files=off
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quartus_map minsoc_top --write_settings_files=off
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$(BUILD_SUPPORT)/minsoc_top.fit.summary: $(BUILD_SUPPORT)/minsoc_top.map.summary
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quartus_fit $(QSF_FILE) --write_Settings_files=off --pack_register=minimize_area
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minsoc_top.fit.summary: minsoc_top.map.summary
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minsoc_top.sof: $(BUILD_SUPPORT)/minsoc_top.fit.summary
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quartus_fit minsoc_top --write_Settings_files=off --pack_register=minimize_area
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quartus_asm $(QSF_FILE)
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mv $(BUILD_SUPPORT)/*.sof .
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minsoc_top.sof: minsoc_top.fit.summary
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$(BUILD_SUPPORT)/minsoc_top.sta.summary: $(BUILD_SUPPORT)/minsoc_top.fit.summary
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quartus_asm minsoc_top
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quartus_sta $(QSF_FILE)
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minsoc_top.sta.summary: minsoc_top.fit.summary
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$(BUILD_SUPPORT)/minsoc_top.eda.summary: $(BUILD_SUPPORT)/minsoc_top.fit.summary
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quartus_sta minsoc_top
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quartus_eda $(QSF_FILE) --write_settings_files=off
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minsoc_top.eda.summary: minsoc_top.fit.summary
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config: minsoc_top.sof
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quartus_eda minsoc_top --write_settings_files=off
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quartus_pgm -c USB-Blaster -m jtag -o "p;minsoc_top.sof"
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distclean:
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distclean:
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$(RM) *.sof
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$(RM) *.sof
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make clean
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make clean
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clean:
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clean:
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$(RM) *.rpt *.summary *.jdi *.smsg *.pin *.qpf
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$(RM) $(BUILD_SUPPORT)/*.rpt $(BUILD_SUPPORT)/*.summary $(BUILD_SUPPORT)/*.jdi $(BUILD_SUPPORT)/*.smsg $(BUILD_SUPPORT)/*.pin $(BUILD_SUPPORT)/*.qpf
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rm -fr db incremental_db
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$(RM) -r $(BUILD_SUPPORT)/db $(BUILD_SUPPORT)/incremental_db
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$(RM) -r $(BUILD_SUPPORT)/db $(BUILD_SUPPORT)/incremental_db
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$(RM) -r $(BUILD_SUPPORT)/db $(BUILD_SUPPORT)/incremental_db
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