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Line 13... |
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2. Open the project file "MIPS32-Pipelined-Hw.xise" located in the
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2. Open the project file "MIPS32-Pipelined-Hw.xise" located in the
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"Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw" directory. This is
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"Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw" directory. This is
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a Xilinx ISE 14.1 project file.
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a Xilinx ISE 14.1 project file.
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3. Build the hardware project and generate the programming .bit file.
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3. Build the Block RAM core by using the Block Memory Generator in
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the Core Generator. See details below.
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4. Build the hardware project and generate the programming .bit file.
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Send the programming file to the board through Impact (you may need
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Send the programming file to the board through Impact (you may need
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to create a new Impact project file for your system, but no options
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to create a new Impact project file for your system, but no options
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are needed other than the configuration .bit file targeted for the
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are needed other than the configuration .bit file targeted for the
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Virtex-5 device). A default program built into the BRAM will print
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Virtex-5 device). A default program built into the BRAM will print
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a hello message to the LCD screen.
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a hello message to the LCD screen.
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Alternatively, a pre-built .bit file is located in the
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Alternatively, a pre-built .bit file is located in the
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"Hardware/XUPV5-LX110T_SoC" directory.
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"Hardware/XUPV5-LX110T_SoC" directory. It is timed conservatively
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at 33 MHz (66 MHz bus).
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4. Compile any of the software demos located in "Software/demos" using
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5. Compile any of the software demos located in "Software/demos" using
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the Makefile included with the demo. One of the output files from
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the Makefile included with the demo. One of the output files from
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the compilation will have a .xum extension. This is a binary file that
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the compilation will have a .xum extension. This is a binary file that
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contains the code and data for the program. Use the XUM Bootloader
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contains the code and data for the program. Use the XUM Bootloader
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software (Windows) to send the .xum file over a serial port to the
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software (Windows) to send the .xum file over a serial port to the
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FPGA. When the program is sent, the CPU will reset and run it.
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FPGA. When the program is sent, the CPU will reset and run it.
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Rebuilding the Block RAM
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Rebuilding the Block RAM
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------------------------
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------------------------
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If you need to recreate the Block RAM core for any reason, the following
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The following settings will allow you to build the Block RAM module
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settings will allow you to do it (assuming Xilinx Block Memory Generator
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and add a default program to it assuming Xilinx Block Memory Generator
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version 7.1): True Dual Port RAM, Common Clock, Byte Write Enable of 8
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version 7.1): True Dual Port RAM, Common Clock, Byte Write Enable of 8
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bits, Write/Read width of 32 bits, Write depth of 151552 (for full
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bits, Write/Read width of 32 bits, Write depth of 151552 (for full
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592 KB), Always Enabled, same options for port B, Register Port A Output
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592 KB), Always Enabled, same options for port B, Register Port A Output
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of Memory Primitives AND Memory Core (for 2R version, this can be
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of Memory Primitives AND Memory Core (for 2R version, this can be
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customized), same settings for Port B, fill remaining locations with
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customized), same settings for Port B, fill remaining locations with
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