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URL https://opencores.org/ocsvn/mips32r1/mips32r1/trunk

Subversion Repositories mips32r1

[/] [mips32r1/] [trunk/] [Hardware/] [XUPV5-LX110T_SoC/] [MIPS32-Pipelined-Hw/] [src/] [MIPS32/] [Hazard_Detection.v] - Diff between revs 7 and 9

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Rev 7	Rev 9
Line 29...	Line 29...
`input [4:0] EX_Rs,`	`input [4:0] EX_Rs,`
`input [4:0] EX_Rt,`	`input [4:0] EX_Rt,`
`input [4:0] EX_RtRd,`	`input [4:0] EX_RtRd,`
`input [4:0] MEM_RtRd,`	`input [4:0] MEM_RtRd,`
`input [4:0] WB_RtRd,`	`input [4:0] WB_RtRd,`
`input ID_Link,`
`input EX_Link,`	`input EX_Link,`
`input EX_RegWrite,`	`input EX_RegWrite,`
`input MEM_RegWrite,`	`input MEM_RegWrite,`
`input WB_RegWrite,`	`input WB_RegWrite,`
`input MEM_MemRead,`	`input MEM_MemRead,`

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